Aggiunti ShiftLeft e ZeroCounter
This commit is contained in:
@@ -98,11 +98,11 @@
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL">
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@@ -110,7 +110,7 @@
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="SumDataAdapterTest.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="266"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="266"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="266"/>
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@@ -139,6 +139,24 @@
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="279"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="279"/>
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</file>
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<file xil_pn:name="ZeroCounter.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="ZeroCounterTest.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="255"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="255"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="255"/>
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</file>
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<file xil_pn:name="ShiftLeft.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="UTILS.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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<properties>
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@@ -397,8 +415,8 @@
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<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SumDataAdapterTest" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SumDataAdapterTest" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ZeroCounterTest" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ZeroCounterTest" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
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@@ -417,7 +435,7 @@
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<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SumDataAdapterTest" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ZeroCounterTest" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
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@@ -473,7 +491,7 @@
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|SumDataAdapterTest|behavior" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|ZeroCounterTest|behavior" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
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80
ShiftLeft.vhd
Normal file
80
ShiftLeft.vhd
Normal file
@@ -0,0 +1,80 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.UTILS.ALL;
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entity ShiftLeft48 is
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port(
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N : in std_logic_vector(47 downto 0);
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PLACES : in std_logic_vector(8 downto 0);
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RESULT : out std_logic_vector(47 downto 0)
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);
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end ShiftLeft48;
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architecture ShiftLeftArch of ShiftLeft48 is
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begin
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shift_process: process (N, PLACES)
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variable POSSIBLE_SHIFTS : ARRAY_OF_STD_LOGIC48;
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begin
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case PLACES is
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when "000000000" => RESULT <= N( 47 downto 0 );
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when "000000001" => RESULT <= N( 46 downto 0 ) & "0";
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when "000000010" => RESULT <= N( 45 downto 0 ) & "00";
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when "000000011" => RESULT <= N( 44 downto 0 ) & "000";
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when "000000100" => RESULT <= N( 43 downto 0 ) & "0000";
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when "000000101" => RESULT <= N( 42 downto 0 ) & "00000";
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when "000000110" => RESULT <= N( 41 downto 0 ) & "000000";
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when "000000111" => RESULT <= N( 40 downto 0 ) & "0000000";
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when "000001000" => RESULT <= N( 39 downto 0 ) & "00000000";
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when "000001001" => RESULT <= N( 38 downto 0 ) & "000000000";
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when "000001010" => RESULT <= N( 37 downto 0 ) & "0000000000";
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when "000001011" => RESULT <= N( 36 downto 0 ) & "00000000000";
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when "000001100" => RESULT <= N( 35 downto 0 ) & "000000000000";
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when "000001101" => RESULT <= N( 34 downto 0 ) & "0000000000000";
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when "000001110" => RESULT <= N( 33 downto 0 ) & "00000000000000";
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when "000001111" => RESULT <= N( 32 downto 0 ) & "000000000000000";
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when "000010000" => RESULT <= N( 31 downto 0 ) & "0000000000000000";
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when "000010001" => RESULT <= N( 30 downto 0 ) & "00000000000000000";
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when "000010010" => RESULT <= N( 29 downto 0 ) & "000000000000000000";
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when "000010011" => RESULT <= N( 28 downto 0 ) & "0000000000000000000";
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when "000010100" => RESULT <= N( 27 downto 0 ) & "00000000000000000000";
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when "000010101" => RESULT <= N( 26 downto 0 ) & "000000000000000000000";
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when "000010110" => RESULT <= N( 25 downto 0 ) & "0000000000000000000000";
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when "000010111" => RESULT <= N( 24 downto 0 ) & "00000000000000000000000";
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when "000011000" => RESULT <= N( 23 downto 0 ) & "000000000000000000000000";
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when "000011001" => RESULT <= N( 22 downto 0 ) & "0000000000000000000000000";
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when "000011010" => RESULT <= N( 21 downto 0 ) & "00000000000000000000000000";
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when "000011011" => RESULT <= N( 20 downto 0 ) & "000000000000000000000000000";
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when "000011100" => RESULT <= N( 19 downto 0 ) & "0000000000000000000000000000";
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when "000011101" => RESULT <= N( 18 downto 0 ) & "00000000000000000000000000000";
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when "000011110" => RESULT <= N( 17 downto 0 ) & "000000000000000000000000000000";
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when "000011111" => RESULT <= N( 16 downto 0 ) & "0000000000000000000000000000000";
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when "000100000" => RESULT <= N( 15 downto 0 ) & "00000000000000000000000000000000";
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when "000100001" => RESULT <= N( 14 downto 0 ) & "000000000000000000000000000000000";
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when "000100010" => RESULT <= N( 13 downto 0 ) & "0000000000000000000000000000000000";
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when "000100011" => RESULT <= N( 12 downto 0 ) & "00000000000000000000000000000000000";
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when "000100100" => RESULT <= N( 11 downto 0 ) & "000000000000000000000000000000000000";
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when "000100101" => RESULT <= N( 10 downto 0 ) & "0000000000000000000000000000000000000";
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when "000100110" => RESULT <= N( 9 downto 0 ) & "00000000000000000000000000000000000000";
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when "000100111" => RESULT <= N( 8 downto 0 ) & "000000000000000000000000000000000000000";
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when "000101000" => RESULT <= N( 7 downto 0 ) & "0000000000000000000000000000000000000000";
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when "000101001" => RESULT <= N( 6 downto 0 ) & "00000000000000000000000000000000000000000";
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when "000101010" => RESULT <= N( 5 downto 0 ) & "000000000000000000000000000000000000000000";
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when "000101011" => RESULT <= N( 4 downto 0 ) & "0000000000000000000000000000000000000000000";
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when "000101100" => RESULT <= N( 3 downto 0 ) & "00000000000000000000000000000000000000000000";
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when "000101101" => RESULT <= N( 2 downto 0 ) & "000000000000000000000000000000000000000000000";
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when "000101110" => RESULT <= N( 1 downto 0 ) & "0000000000000000000000000000000000000000000000";
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when "000101111" => RESULT <= N( 0 ) & "00000000000000000000000000000000000000000000000";
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when others => RESULT <= "000000000000000000000000000000000000000000000000";
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end case;
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end process;
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end ShiftLeftArch;
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63
UTILS.vhd
Normal file
63
UTILS.vhd
Normal file
@@ -0,0 +1,63 @@
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--
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-- Package File Template
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--
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-- Purpose: This package defines supplemental types, subtypes,
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-- constants, and functions
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--
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-- To use any of the example code shown below, uncomment the lines and modify as necessary
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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package UTILS is
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-- type <new_type> is
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-- record
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-- <type_name> : std_logic_vector( 7 downto 0);
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-- <type_name> : std_logic;
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-- end record;
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--
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-- Declare constants
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--
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-- constant <constant_name> : time := <time_unit> ns;
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-- constant <constant_name> : integer := <value;
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--
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-- Declare functions and procedure
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--
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-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
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-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
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--
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type ARRAY_OF_STD_LOGIC48 is array (0 to 512) of std_logic_vector(47 downto 0);
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end UTILS;
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package body UTILS is
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---- Example 1
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-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
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-- variable <variable_name> : <type_declaration>;
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-- begin
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-- <variable_name> := <signal_name> xor <signal_name>;
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-- return <variable_name>;
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-- end <function_name>;
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---- Example 2
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-- function <function_name> (signal <signal_name> : in <type_declaration>;
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-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
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-- begin
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-- if (<signal_name> = '1') then
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-- return <signal_name>;
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-- else
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-- return 'Z';
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-- end if;
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-- end <function_name>;
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---- Procedure Example
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-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
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--
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-- begin
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--
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-- end <procedure_name>;
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end UTILS;
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60
ZeroCounter.vhd
Normal file
60
ZeroCounter.vhd
Normal file
@@ -0,0 +1,60 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity ZeroCounter is
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generic(
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BITCOUNT : integer := 8;
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RES_BITCOUNT : integer := 3 -- MUST BE >= CEIL( LOG2( BITCOUNT ) )
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);
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port(
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X : in std_logic_vector( (BITCOUNT-1) downto 0 );
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Z_COUNT : out std_logic_vector( (RES_BITCOUNT-1) downto 0 );
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ALL_ZEROS : out std_logic
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);
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end ZeroCounter;
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architecture ZeroCounterArch of ZeroCounter is
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begin
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ZEROCOUNT_PROCESS: process (X)
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variable ZC: std_logic_vector((RES_BITCOUNT-1) downto 0);
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variable BIN_N: std_logic_vector((RES_BITCOUNT-1) downto 0);
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variable PART_ZC: std_logic_vector((BITCOUNT-1) downto 0);
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begin
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ZC := ((RES_BITCOUNT-1) downto 0 => '0');
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PART_ZC := ((BITCOUNT-1) downto 0 => '1');
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for N in 1 to (BITCOUNT-1) loop
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-- compute partial logic to add to result's '1' bits
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for p_i in (BITCOUNT-1) downto (BITCOUNT-N) loop
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PART_ZC(N) := PART_ZC(N) and (not X(p_i));
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end loop;
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PART_ZC(N) := PART_ZC(N) and X(BITCOUNT-1-N);
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-- add partial logic to result
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BIN_N := std_logic_vector(to_unsigned(N, BIN_N'length));
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for res_i in (RES_BITCOUNT-1) downto 0 loop
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if ( BIN_N(res_i) = '1' ) then
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ZC(res_i) := ZC(res_i) or PART_ZC(N);
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end if;
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end loop;
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end loop;
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Z_COUNT <= ZC;
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end process;
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ALLZERO_PROCESS: process (X)
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variable AZ : std_logic;
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begin
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AZ := '1';
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for i in X'range loop
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AZ := AZ and (not X(i));
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end loop;
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ALL_ZEROS <= AZ;
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end process;
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end ZeroCounterArch;
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79
ZeroCounterTest.vhd
Normal file
79
ZeroCounterTest.vhd
Normal file
@@ -0,0 +1,79 @@
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY ZeroCounterTest IS
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END ZeroCounterTest;
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ARCHITECTURE behavior OF ZeroCounterTest IS
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COMPONENT ZeroCounter
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PORT(
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||||
X : IN std_logic_vector(7 downto 0);
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Z_COUNT : OUT std_logic_vector(2 downto 0);
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ALL_ZEROS : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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||||
signal X : std_logic_vector(7 downto 0) := (others => '0');
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--Outputs
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||||
signal Z_COUNT : std_logic_vector(2 downto 0);
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||||
signal ALL_ZEROS : std_logic;
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||||
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constant clock_period : time := 10 ns;
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||||
signal clock: std_logic;
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||||
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BEGIN
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||||
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||||
-- Instantiate the Unit Under Test (UUT)
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||||
uut: ZeroCounter PORT MAP (
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||||
X => X,
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||||
Z_COUNT => Z_COUNT,
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ALL_ZEROS => ALL_ZEROS
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||||
);
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||||
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||||
-- Clock process definitions
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||||
clock_process :process
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||||
begin
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||||
clock <= '0';
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wait for clock_period/2;
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||||
clock <= '1';
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wait for clock_period/2;
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end process;
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||||
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||||
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stim_proc: process
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||||
begin
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||||
X <= "00000000";
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wait for clock_period;
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||||
X <= "00000001";
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wait for clock_period;
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X <= "00000010";
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wait for clock_period;
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X <= "00000100";
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wait for clock_period;
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||||
X <= "00001000";
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wait for clock_period;
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X <= "00010000";
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||||
wait for clock_period;
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X <= "00100000";
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||||
wait for clock_period;
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X <= "01000000";
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wait for clock_period;
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X <= "10000000";
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wait for clock_period;
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X <= "00100110";
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wait for clock_period;
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X <= "11111111";
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wait for clock_period;
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X <= "01111111";
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wait for clock_period;
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X <= "00111111";
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||||
wait for clock_period;
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||||
X <= "00101111";
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||||
wait for clock_period;
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||||
end process;
|
||||
|
||||
END;
|
||||
BIN
ZeroCounterTest_isim_beh.exe
Executable file
BIN
ZeroCounterTest_isim_beh.exe
Executable file
Binary file not shown.
BIN
ZeroCounterTest_isim_beh.wdb
Normal file
BIN
ZeroCounterTest_isim_beh.wdb
Normal file
Binary file not shown.
30
fuse.log
30
fuse.log
@@ -1,11 +1,23 @@
|
||||
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj work.SumDataAdapterTest
|
||||
ISim P.20160913 (signature 0xfbc00daa)
|
||||
Number of CPUs detected in this system: 1
|
||||
Turning on mult-threading, number of parallel sub-compilation jobs: 0
|
||||
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_beh.prj work.ZeroCounterTest
|
||||
ISim P.20131013 (signature 0xfbc00daa)
|
||||
Number of CPUs detected in this system: 4
|
||||
Turning on mult-threading, number of parallel sub-compilation jobs: 8
|
||||
Determining compilation order of HDL files
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/ShiftRight.vhd" into library work
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapter.vhd" into library work
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" into library work
|
||||
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounter.vhd" into library work
|
||||
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest.vhd" into library work
|
||||
Starting static elaboration
|
||||
ERROR:HDLCompiler:410 - "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has 30 elements ; expected 31
|
||||
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit sumdataadaptertest in library work failed
|
||||
Completed static elaboration
|
||||
Fuse Memory Usage: 95772 KB
|
||||
Fuse CPU Usage: 1030 ms
|
||||
Compiling package standard
|
||||
Compiling package std_logic_1164
|
||||
Compiling package numeric_std
|
||||
Compiling architecture zerocounterarch of entity ZeroCounter [\ZeroCounter(8,3)\]
|
||||
Compiling architecture behavior of entity zerocountertest
|
||||
Time Resolution for simulation is 1ps.
|
||||
Waiting for 1 sub-compilation(s) to finish...
|
||||
Compiled 6 VHDL Units
|
||||
Built simulation executable /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe
|
||||
Fuse Memory Usage: 665500 KB
|
||||
Fuse CPU Usage: 1100 ms
|
||||
GCC CPU Usage: 170 ms
|
||||
|
||||
@@ -5,11 +5,5 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="error" file="HDLCompiler" num="410" delta="unknown" >"/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has <arg fmt="%d" index="1">30</arg> elements ; expected <arg fmt="%d" index="2">31</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="Simulator" num="777" delta="unknown" >Static elaboration of top level VHDL design unit <arg fmt="%s" index="1">sumdataadaptertest</arg> in library <arg fmt="%s" index="2">work</arg> failed
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
||||
@@ -1 +1 @@
|
||||
-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj" "work.SumDataAdapterTest"
|
||||
-intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest_beh.prj" "work.ZeroCounterTest"
|
||||
|
||||
Reference in New Issue
Block a user