lucacuzzocrea/IEEE754Adder
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Aggiunti ShiftLeft e ZeroCounter

Browse Source
This commit is contained in:
Luca Cuzzocrea
2019-09-08 15:20:19 +02:00
parent 0250f39c47
commit 5a2605e685
11 changed files with 331 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
fuse.log
View File

@@ -1,11 +1,23 @@
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj work.SumDataAdapterTest
ISim P.20160913 (signature 0xfbc00daa)
Number of CPUs detected in this system: 1
Turning on mult-threading, number of parallel sub-compilation jobs: 0
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_beh.prj work.ZeroCounterTest
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/ShiftRight.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapter.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounter.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest.vhd" into library work
Starting static elaboration
ERROR:HDLCompiler:410 - "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has 30 elements ; expected 31
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit sumdataadaptertest in library work failed
Completed static elaboration
Fuse Memory Usage: 95772 KB
Fuse CPU Usage: 1030 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling architecture zerocounterarch of entity ZeroCounter [\ZeroCounter(8,3)\]
Compiling architecture behavior of entity zerocountertest
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 6 VHDL Units
Built simulation executable /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe
Fuse Memory Usage: 665500 KB
Fuse CPU Usage: 1100 ms
GCC CPU Usage: 170 ms