Aggiunto controllo risultato NaN
This commit is contained in:
lucacuzzocrea committed
1 parent
a1b9650580
commit
47cc74e0d0
18 files changed
+377
-106
No files matched your search
+20
-12
@@ -24,7 +24,10 @@
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SpecialCasesCheck.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SpecialCasesCheck.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SpecialCasesCheck.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SpecialCasesCheck.ngr"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesCheck.prj"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SpecialCasesCheck.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SpecialCasesCheck.syr"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SpecialCasesCheck.xst"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="SpecialCasesCheck_envsettings.html"/>
|
||||
@@ -83,11 +86,11 @@
|
||||
<transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1566052458">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1566052805" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3534754566125264796" xil_pn:start_ts="1566052805">
|
||||
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1167941000477774584" xil_pn:start_ts="1566059978">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1566052805" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8013279211492191508" xil_pn:start_ts="1566052805">
|
||||
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8700953375414271688" xil_pn:start_ts="1566059978">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
@@ -95,7 +98,7 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1566052805" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1039519274070425884" xil_pn:start_ts="1566052805">
|
||||
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2391194399288376768" xil_pn:start_ts="1566059978">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
@@ -103,21 +106,22 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1566052805" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4325541895085471050" xil_pn:start_ts="1566052805">
|
||||
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1647368633314702702" xil_pn:start_ts="1566059978">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1566054140" xil_pn:in_ck="-4395428264884964098" xil_pn:name="TRANEXT_xstsynthesize_spartan3" xil_pn:prop_ck="2853843150675393866" xil_pn:start_ts="1566054134">
|
||||
<transform xil_pn:end_ts="1566060235" xil_pn:in_ck="-3235492353642026610" xil_pn:name="TRANEXT_xstsynthesize_spartan3" xil_pn:prop_ck="-5588158190480725594" xil_pn:start_ts="1566060230">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="TypeCheck.lso"/>
|
||||
<outfile xil_pn:name="TypeCheck.ngc"/>
|
||||
<outfile xil_pn:name="SpecialCasesCheck.lso"/>
|
||||
<outfile xil_pn:name="SpecialCasesCheck.ngc"/>
|
||||
<outfile xil_pn:name="SpecialCasesCheck.ngr"/>
|
||||
<outfile xil_pn:name="SpecialCasesCheck.prj"/>
|
||||
<outfile xil_pn:name="SpecialCasesCheck.stx"/>
|
||||
<outfile xil_pn:name="SpecialCasesCheck.syr"/>
|
||||
<outfile xil_pn:name="SpecialCasesCheck.xst"/>
|
||||
<outfile xil_pn:name="SpecialCasesCheck_xst.xrpt"/>
|
||||
<outfile xil_pn:name="TypeCheck.ngr"/>
|
||||
<outfile xil_pn:name="TypeCheck.prj"/>
|
||||
<outfile xil_pn:name="TypeCheck.stx"/>
|
||||
<outfile xil_pn:name="TypeCheck.syr"/>
|
||||
<outfile xil_pn:name="TypeCheck.xst"/>
|
||||
<outfile xil_pn:name="TypeCheck_xst.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
@@ -125,11 +129,15 @@
|
||||
<transform xil_pn:end_ts="1566052811" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-2497314214044977511" xil_pn:start_ts="1566052811">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1566052856" xil_pn:in_ck="-1179315243053685338" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7709254264864982892" xil_pn:start_ts="1566052852">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="TypeCheck.bld"/>
|
||||
<outfile xil_pn:name="TypeCheck.ngd"/>
|
||||
|
||||
+13
-8
@@ -17,6 +17,10 @@
|
||||
<files>
|
||||
<file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
</files>
|
||||
@@ -142,8 +146,9 @@
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|TypeCheck|TypeCheckArch" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SpecialCasesCheck|SpecialCasesCheckArch" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="SpecialCasesCheck.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SpecialCasesCheck" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -207,7 +212,7 @@
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="TypeCheck" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
@@ -222,10 +227,10 @@
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="TypeCheck_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="TypeCheck_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="TypeCheck_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="TypeCheck_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SpecialCasesCheck_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="SpecialCasesCheck_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SpecialCasesCheck_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SpecialCasesCheck_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
@@ -251,7 +256,7 @@
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="TypeCheck" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
@@ -2,3 +2,6 @@ xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn
|
||||
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
@@ -0,0 +1,3 @@
|
||||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.6e
|
||||
$bfx55=4:3CE\XZ5X=12>58682996D@_UU8Z867=87>0:=>?2::30>>78920NX]PIODL=>EHEDC_XHJ8;BPFEQCC92O?7HONA39EA1=ANOO:7J=4GOF2?L4<A980E<<4I308M62<AK_M56GAIUQWEQC03EELENOC4:NVP72<D\^886BZT508J74<F=80B;94NDVTKWM63F>0CO[Ic:R-657499;8SA:4P@PWe>VNFVH^_DJWb:RJJZDR[GKFI;5\OTP@A47<[yohelbLargpGmcdc=1_U]Kl;TQFVZPN[@HGI45YIDU\P\VB<2R7<3;4X=33:0=_48;596V313<6?]:6;7?0T1?;>49[8439=2R7=;0:;Y>23;3<P5;3285W<0;=0>^;97?0T1<?>49[8779=2R7>?0:;Y>17;3<P58?285W<37=1>^;:?4>7U2=7?78\94?6<1S0?714:Z?6;3<P59;2:5W<2394;3<P59:295W<2<7?]:36=1S080;;Y>5:1=_4>4?7U27>59[8<86l2RB@D@W-YFA$5(6(Z^^N->!1!CPGLO13QY_@DL8;YQW[BHC02RT<RGMUG;8\Z77W@H^J45W_03\MGSA12RT=?QFBTD:?]Y6;VCIYK74X^37[LDRN01SS<;PICWE=>^X9?UBNXH6;Y]23ZOE]O30TR?7_H@VB<=_W83TEO[I8:Z\5ZOE]O30TR<?_H@VB<=_W;;TEO[I9:Z\67YNJ\L27UQ=3^KAQC?<PV8?SDLZF89[[73XAK_M56VP27]JFP@>3QU9;RGMUG;8\Z4?W@H^J45W_3;\MGSA02RT>RGMUG;8\Z57W@H^J45W_23\MGSA02RT?RGMUG:8\Z2XAK_M46VP5^KAQC><PV<TEO[I8:Z\3ZOE]O20TR6PICWE<>^X1VCIYK84Xe`\Ma773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee?6V|t59Z85823P6:<3;4Y=32:0=^488596W312<6?\:6<7?0U1?:>49Z8409=2S7=:0:;X>2<;3<Q5;2295V<0<6?\:587?0U1<>>49Z8749=2S7>>0:;X>10;3<Q58>285V<34=1>_;:>4>7T2=8?78]94>6=1R0?0:;X>04;1<Q59:6=0:;X>05;2<Q59586W34?68]939<2S7:3:4Y=5=0>_;07>0U1718:[\4ZOE]O30UR??_H@VB<=^W8;TEO[I9:[\57YNJ\L27TQ>3^KAQC?<QV;?SDLZF89Z[43XAK_M56WP17]JFP@>3PU:;RGMUG;8]Z7?W@H^J45V_0;\MGSA02ST=RGMUG;8]Z47W@H^J45V_33\MGSA12ST>?QFBTD:?\Y5;VCIYK74Y^07[LDRN01RS?;PICWE=>_X:?UBNXH6;X]13ZOE]O30UR<7_H@VB<=^W;3TEO[I8:[\6ZOE]O30UR=?_H@VB<=^W:;TEO[I8:[\7ZOE]O20UR:PICWE<>_X=VCIYK64Y^4\MGSA02ST;RGMUG:8]Z>XAK_M46WP9^KAQC3<azDjb55fsOcm556?3`yEmc??599jwKgi98<37d}Aao315==n{Gke=>?7;hqMek708j1bCoa162\WR6?3`yEmc?7399jwKgi91237d}Aao03=f=n{Gke>=7PSV24?luIig8=n6g|N`l12ZUP8>1bCoa3448mvHff==0e~@nn524?luIig>:;6g|N`l552=n{Gke4884irLbj<1<azDjb4>n;hqMekYHJ\L=7d}Uesma?lu]m{eTCO[Ie:z`7v37%<'{}?>79:{@l`el'N>27tMgebi,C<{GHy8ho6NOx369B?4=9rY<6;h51g827171>8094?>>{o4g>4=i>l0=7)8l:5;8yV0=>o0:j7?<40455?4?:990h?:50;395~U02?l1=k4>353524<50;::7{Z=3;295?7=1hqX;78i:0d95626>?;1>5<?1:&13?723-8;6no4b3694?252<k15luG279'60<5<2P>6?u?:08~kg7=831do54?::k75?6=,;818=5a2083?>o4n3:1(?<5419m64<632c8h7>5$30905=i:80976g<c;29 74=<91e><4<;:k0f?6=,;818=5a2087?>o4i3:1(?<5419m64<232c857>5$30905=i:80=76g<8;29 74=<91e><48;:k03?6=,;818=5a208;?>o4>3:1(?<5419m64<>32c897>5$30905=i:80j76g<4;29 74=<91e><4m;:k06?6=,;818=5a208`?>o493:1(?<5419m64<c32c8<7>5$30905=i:80n76g=f;29 74=<91e><4i;:k1a?6=,;818=5a20824>=n:m0;6)<=:528j77=9810e?m50;&16?273g8:6<<4;h0a>5<#:;0?<6`=1;30?>o5i3:1(?<5419m64<6<21b>44?:%01>16<f;;1=854i5:94?"5:3>;7c<>:048?l20290/>?4;0:l15?7032c?:7>5$30905=i:80:465f4483>!452=:0b??51898m12=83.9>7:?;o02>4g<3`>86=4+23874>h593;i76g;2;29 74=<91e><4>c:9j7`<72-8969>4n3395a=<a:91<7*=2;63?k4628o07d<7:18'67<382d9=7?i;:k;=?6=,;81455a2083?>o??3:1(?<5899m64<632c397>5$309<==i:80976g74;29 74=011e><4<;:k;7?6=,;81455a2087?>o?:3:1(?<5899m64<232c3=7>5$309<==i:80=76g70;29 74=011e><48;:k4b?6=,;81455a208;?>o0m3:1(?<5899m64<>32c<h7>5$309<==i:80j76g8c;29 74=011e><4m;:k4e?6=,;81455a208`?>o013:1(?<5899m64<c32c<47>5$309<==i:80n76g87;29 74=011e><4i;:k42?6=,;81455a20824>=n?<0;6)<=:9:8j77=9810e::50;&16?>?3g8:6<<4;h50>5<#:;0346`=1;30?>o0:3:1(?<5899m64<6<21b;<4?:%01>=><f;;1=854i8294?"5:3237c<>:048?l>a290/>?478:l15?7032c3i7>5$309<==i:80:465f8e83>!452120b??51898m=e=83.9>767;o02>4g<3`2i6=4+238;<>h593;i76g7a;29 74=011e><4>c:9j<3<72-896564n3395a=<a>h1<7*=2;:;?k4628o07d9?:18'67<?02d9=7?i;:`7f?6=93:1<v*=5;f8L1g<@;<0cn4?::agg<72<0;6=u+2482<>N3i2B9:6*>4;68mc<722c:<7>5;h32>5<<a881<75`1e83>>{ekj0;684?:1y'60<602B?m6F=6:&20?2<ao0;66g>0;29?l762900e<<50;9l5a<722wio=4?:483>5}#:<0:46F;a:J12>"6<3h0ek4?::k24?6=3`;:6=44i0094?=h9m0;66smc483>0<729q/>84>8:J7e>N5>2.:87l4ig83>>o683:17d?>:188m44=831d=i4?::afc<72<0;6=u+2482<>N3i2B9:6*>4;`8mc<722c:<7>5;h32>5<<a881<75`1e83>>{ek80;684?:1y'60<602B?m6F=6:&20?d<ao0;66g>0;29?l762900e<<50;9l5a<722wio?4?:283>5}#:<0::6F;a:J12>"6<320ek4?::k24?6=3f;o6=44}ca0>5<2290;w)<::0:8L1g<@;<0(<:5b:ke>5<<a8:1<75f1083>>o6:3:17b?k:188yge3290>6=4?{%06>4><@=k0D?84$069f>oa2900e<>50;9j54<722c:>7>5;n3g>5<<uki=6=4::183!422820D9o4H348 42=j2cm6=44i0294?=n980;66g>2;29?j7c2900qol=:187>5<7s-8>6<94H5c8L70<,8>1m6gi:188m46=831b=<4?::m2`?6=3thi?7>55;294~"5=3;37E:n;I05?!732k1bj7>5;h33>5<<a8;1<75f1383>>i6l3:17plm4;291?6=8r.997?7;I6b?M413-;?6o5ff;29?l772900e<?50;9j57<722e:h7>5;|`a1?6==3:1<v*=5;3;?M2f3A8=7)?;:c9jb?6=3`;;6=44i0394?=n9;0;66a>d;29?xde>3:197>50z&11?7?3A>j7E<9;%37>g=nn3:17d??:188m47=831b=?4?::m2`?6=3thi57>55;294~"5=3;37E:n;I05?!732=1bj7>5;h33>5<<a8;1<75f1383>>i6l3:17plma;291?6=8r.997?7;I6b?M413-;?695ff;29?l772900e<?50;9j57<722e:h7>5;|`50?6=:3:1<v*=5;30?M2f3A8=7dk50;9l5a<722wi:>4?:383>5}#:<0:?6F;a:J12>ob2900c<j50;9~f37=8381<7>t$37956=O<h1C>;5fe;29?j7c2900qo8?:181>5<7s-8>6<=4H5c8L70<al0;66a>d;29?xd2n3:1>7>50z&11?743A>j7E<9;hg94?=h9m0;66sm5d83>7<729q/>84>3:J7e>N5>2cn6=44o0f94?=zj<n1<7<50;2x 73=9:1C8l5G279ja?6=3f;o6=44}c7`>5<5290;w)<::018L1g<@;<0eh4?::m2`?6=3th>n7>52;294~"5=3;87E:n;I05?lc=831d=i4?::a1d<72;0;6=u+24827>N3i2B9:6gj:188k4b=831vn8750;094?6|,;?1=>5G4`9K63=nm3:17b?k:188yg3?29096=4?{%06>45Line truncated
|
||||
@@ -0,0 +1,3 @@
|
||||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.6e
|
||||
$ccx74=(`fgn#A{la.KPA*OBML=>8Ljkes-Pt`enieIjh}Lhdah*snc9918>7GAPTV9J956294:<6==:HLSQQ<_4:;1<3??;209MKVR\3S7?<4?>`906?H;;80;2l5<2;Z?74<76h18>7W33083:g=4{<:{}?>7-468EKB5>2KEH?L>6:CM@1D6<2KEH564BTQ\MK@H12IDA@G[TDF4?FTBI]OO=6I<;FLG<>AXadzTK<<4I108M44<A;80E><4I508M04<A?80E:=4IOD`?LHAW`g{SD@I1d9HA@VX@@OYM_MGY69OKBODIE>0B1>15:L?55823G6:=3;4N=31:0=I489596@315<6?K:6=7?0B1?9>49M8419=2D7=50:;O>2=;2<F5;596@321<6?K:597?0B1<=>49M8759=2D7>90:;O>11;3<F58=285A<35=1>H;:14>7C2=9?68J949=2D7?=08;O>05?69=2D7?<0;;O>0:1=I4=4?7C2:>59M83833G6<295A<9<7?K:>6:1EmCm4N`L\mhvXFhD:=6A<;NP17>IU;:1D^9=4OS:`?U(5889:<<=PL59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ3:PWHg=TANH^_RGAFNc8WLAXJ\YBHUl4SHE\FPUIIDO:=6]ebkbhFgtmzIcine>;U68P\VB02^Te`~PT0a8PZrjxVey<=>?d:V\phvXg{:;<=?k;U]wiuYhz9:;<?j4T^vntZiu89:;?<>4T^vntZiu89:;Sdcc:V\phvXg{:;<<j4T^vntZiu89::=i5[_uos[jt789;9h6ZPtlr\kw67889:<6ZPtlr\kw6788Uba}74TxrfGmcdc01]EHYPTXRF0>^;87?0T1??>49[8479=2R7=?0:;Y>27;3<P5;?285W<07=1>^;9?4>7U2>7?78\97?6<1S0<714:Z?5;3<P58;285W<33=1>^;:;4>7U2=3?78\9436<1S0?;15:Z?63823Q69;3;4X=0;:0=_4;3586V32?78\9576>1S0>?50?78\9566=1S0>0;;Y>7:1=_4<4?7U29>59[82833Q63295W<8<2`>^ND@DS!UJM 1,2$VRRJ):%=-O\CHK5?]USD@H<7U][_FLG5`=_[]UBA]BJMDLWEQOHFVIDB^Z]AHLWW46<PZ^T^YBPPSMSAWR^>2RonRGk119[`hYJiceyZh||inl24>^ceVGbbb|Yesqjkk5<Pz~27U}{GLmgai2<Q5:596W311<6?\:697?0U1?=>49Z8459=2S7=90:;X>21;3<Q5;=285V<05=1>_;914>7T2>9?68]979=2S7>=0:;X>15;3<Q589285V<31=1>_;:=4>7T2=5?78]9416<1R0?915:[?6=823P6953:4Y=0=1>_;;94<7T2<1;2=1>_;;84?7T2<>59Z81833P6>295V<7<7?\:06=1R050;;X>::0=n{Gkeh6g|N`l\ekb789:9<6g|N`l\ekb789:Te`~PirLbjZgil9:;<<j4irLbjZgil9:;=?>4irLbjZgil9:;=Rgbp^kpJdhXign;<=?>119jwKgiW`g{Sd}Aao35?lu]m{em7~azrbg\bljbfhgnh6}`usaf[ioimgh=7uMgebi7?}Oin=1sBl`j;ya0w06*=$zz>=69;xAkafm33pCej95vN`l~DEv5:;1KLu67:G81>4}Tm32<69851262237=:18;=v`75;38j=0=>2.3879i;|Qg>=1=<?0:?9?96081<7643m>n6=4>:0yPa?>02=<1=>:>67396=4792|M8l4?:082>5}Tm32<69851262237=:18;=6*:d;3g?!202>1i8h4?:5092?2?sE296<u+468a2>{K0:0:w)l>:19~ 06=<l1Qo7<t2;19y_2e2;q>6;4ro`c94?=hj90;66g87;29 1?=??1e854?;:k41?6=,=31;;5a4982?>o0;3:1(975779m0=<532c<>7>5$5;933=i<10876g81;29 1?=??1e854;;:k44?6=,=31;;5a4986?>o1n3:1(975779m0=<132c=i7>5$5;933=i<10<76g9d;29 1?=??1e8547;:k5g?6=,=31;;5a498:?>o1j3:1(975779m0=<f32c=m7>5$5;933=i<10i76g98;29 1?=??1e854l;:k53?6=,=31;;5a498g?>o1>3:1(975779m0=<b32c=97>5$5;933=i<10m76g94;29 1?=??1e854>0:9j26<72->26:84n5:954=<a?81<7*;9;55?k2?28807d8>:18'0<<0>2d?47?<;:k54?6=,=31;;5a49820>=n=o0;6):6:648j1>=9<10e:k50;&7=?113g>36<84;h5g>5<#<00<:6`;8;34?>o0k3:1(975779m0=<6021b;o4?:%6:>20<f=21=454i6c94?"313==7c:7:0c8?l1>290/84486:l7<?7e32c<47>5$5;933=i<10:o65f7583>!2>2><0b9651e98m3?=83.?5799;o6;>4c<3`?n6=4+48842>h303;m76gn2;29 1?=i81e854?;:kb4?6=,=31m<5a4982?>o>m3:1(975a09m0=<532c2h7>5$5;9e4=i<10876g6c;29 1?=i81e854;;:k:f?6=,=31m<5a4986?>o>i3:1(975a09m0=<132c257>5$5;9e4=i<10<76g68;29 1?=i81e8547;:k:3?6=,=31m<5a498:?>o>>3:1(975a09m0=<f32c297>5$5;9e4=i<10i76g63;29 1?=i81e854l;:k:6?6=,=31m<5a498g?>o>93:1(975a09m0=<b32c2<7>5$5;9e4=i<10m76g7f;29 1?=i81e854>0:9j<`<72->26l?4n5:954=<a1n1<7*;9;c2?k2?28807d6l:18'0<<f92d?47?<;:k;f?6=,=31m<5a49820>=n0h0;6):6:`38j1>=9<10el750;&7=?g63g>36<84;hc;>5<#<00j=6`;8;34?>of?3:1(975a09m0=<6021bm;4?:%6:>d7<f=21=454i`794?"313k:7c:7:0c8?lg3290/844n1:l7<?7e32cj?7>5$5;9e4=i<10:o65f9g83>!2>2h;0b9651e98m<2=83.?57o>;o6;>4c<3`226=4+488b5>h303;m76l71;295?6=8r.><7??;I:3?j`=831vno=50;01>3<5=rF3>7?tH0a8yI>42;qen?4>d:&a5?6<u-?;68m4Zb824<zR=h1=v:5}n1e>5<<g8k1<75f3683>!2>2:<0b9650:9j70<72->26>84n5:95>=n;:0;6):6:248j1>=:21b??4?:%6:>60<f=21?65f3083>!2>2:<0b9654:9j75<72->26>84n5:91>=n:o0;6):6:248j1>=>21b>h4?:%6:>60<f=21;65f2e83>!2>2:<0b9658:9j6f<72->26>84n5:9=>=n:k0;6):6:248j1>=i21b>l4?:%6:>60<f=21n65f2983>!2>2:<0b965c:9j62<72->26>84n5:9`>=n:?0;6):6:248j1>=m21b>84?:%6:>60<f=21j65f2583>!2>2:<0b9651198m75=83.?57=9;o6;>47<3`896=4+48802>h303;976g=1;29 1?=;?1e854>3:9j65<72->26>84n5:951=<a8l1<7*;9;15?k2?28?07d=j:18'0<<4>2d?47?9;:k0`?6=,=31?;5a49823>=n;j0;6):6:248j1>=9110e>l50;&7=?513g>36<74;h1b>5<#<008:6`;8;3b?>o413:1(975379m0=<6j21b?54?:%6:>60<f=21=n54i2694?"3139=7c:7:0f8?l4>290/844<6:l7<?7b32c:i7>5$5;973=i<10:j65m5783>f<42lq/9=4:6:m66?6=3`8h6=44i3`94?=n:h0;66g=8;29?l402900e?850;9j60<722c987>5;h00>5<<a;81<75f2083>>d2;3:157>50z&64?223A2;7d?=:188m45=831b=94?::k21?6=3`;=6=44i0594?=n910;66g>9;29?j262900qo;;:187>5<7s-?;69=4H928m44=831b=>4?::k20?6=3f>:6=44}c76>5<4290;w);?:508L=6<a881<75f1283>>i393:17p}:2;296~X2:27>97:>;|q1g?6=:rT9o63:3;30?xu5j3:1>vP=b:?67?753ty9m7>52z\1e>;2;3;?7p}=8;296~X5027>?7?9;|q13?6=:rT9;63:3;36?xu5>3:1>vP=6:?67?703ty997>52z\11>;2;3;27p}=4;296~X5<27>?7?7;|q17?6=:rT9?63:4;30?xu5:3:1>vP=2:?60?753ty9=7>52z\15>;2<3;?7p}:3;296~;2;3>:70;::008yv332909w0;;:538903=9:1vqo;m:18`>6<bs-?;68l4o4594?=n=;0;66g=0;29?l7a2900e>k50;9j7a<722c8o7>5;h1a>5<<a:k1<75f3883>>o403:17d=;:188f0>=8331<7>t$42900=O091b=?4?::k27?6=3`;?6=44i0794?=n9?0;66g>7;29?l7?2900e<750;9l04<722wi944?:583>5}#=90??6F70:k26?6=3`;86=44i0694?=h<80;66sm5`83>6<729q/9=4;2:J;4>o6:3:17d?<:188k17=831v8950;0xZ01<5<k18<5rs4094?4|V<801865129~w76=838pR?>4=4:957=z{8l1<7<t^0d890>=9=1v>k50;0xZ6cLine truncated
|
||||
@@ -1 +1,2 @@
|
||||
vhdl work "TypeCheck.vhd"
|
||||
vhdl work "SpecialCasesCheck.vhd"
|
||||
Whitespace-only changes.
+191
-12
@@ -5,14 +5,14 @@ Parameter TMPDIR set to xst/projnav.tmp
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.04 secs
|
||||
Total CPU time to Xst completion: 0.05 secs
|
||||
|
||||
-->
|
||||
Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.04 secs
|
||||
Total CPU time to Xst completion: 0.05 secs
|
||||
|
||||
-->
|
||||
Reading design: SpecialCasesCheck.prj
|
||||
@@ -107,20 +107,199 @@ Slice Utilization Ratio Delta : 5
|
||||
=========================================================================
|
||||
* HDL Compilation *
|
||||
=========================================================================
|
||||
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" in Library work.
|
||||
Architecture typecheckarch of Entity typecheck is up to date.
|
||||
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work.
|
||||
Entity <typecheck> compiled.
|
||||
Entity <typecheck> (Architecture <typecheckarch>) compiled.
|
||||
ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. Undefined symbol 'std_logic_vector'.
|
||||
ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. std_logic_vector: Undefined symbol (last report in this block)
|
||||
ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. Undefined symbol 'std_logic'.
|
||||
ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. std_logic: Undefined symbol (last report in this block)
|
||||
ERROR:HDLParsers:3010 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 55. Entity SpecialCasesCheck does not exist.
|
||||
Entity <specialcasescheck> compiled.
|
||||
Entity <specialcasescheck> (Architecture <specialcasescheckarch>) compiled.
|
||||
|
||||
=========================================================================
|
||||
* Design Hierarchy Analysis *
|
||||
=========================================================================
|
||||
Analyzing hierarchy for entity <SpecialCasesCheck> in library <work> (architecture <specialcasescheckarch>).
|
||||
|
||||
Analyzing hierarchy for entity <TypeCheck> in library <work> (architecture <typecheckarch>).
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing Entity <SpecialCasesCheck> in library <work> (Architecture <specialcasescheckarch>).
|
||||
Entity <SpecialCasesCheck> analyzed. Unit <SpecialCasesCheck> generated.
|
||||
|
||||
Analyzing Entity <TypeCheck> in library <work> (Architecture <typecheckarch>).
|
||||
Entity <TypeCheck> analyzed. Unit <TypeCheck> generated.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Performing bidirectional port resolution...
|
||||
|
||||
Synthesizing Unit <TypeCheck>.
|
||||
Related source file is "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd".
|
||||
WARNING:Xst:647 - Input <N<31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
Unit <TypeCheck> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <SpecialCasesCheck>.
|
||||
Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd".
|
||||
Unit <SpecialCasesCheck> synthesized.
|
||||
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
Found no macro
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Advanced HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
|
||||
Found no macro
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Low Level Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Optimizing unit <SpecialCasesCheck> ...
|
||||
|
||||
Mapping all equations...
|
||||
Building and optimizing final netlist ...
|
||||
Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 1.
|
||||
|
||||
Final Macro Processing ...
|
||||
|
||||
=========================================================================
|
||||
Final Register Report
|
||||
|
||||
Found no macro
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Partition Report *
|
||||
=========================================================================
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
=========================================================================
|
||||
* Final Report *
|
||||
=========================================================================
|
||||
Final Results
|
||||
RTL Top Level Output File Name : SpecialCasesCheck.ngr
|
||||
Top Level Output File Name : SpecialCasesCheck
|
||||
Output Format : NGC
|
||||
Optimization Goal : Speed
|
||||
Keep Hierarchy : No
|
||||
|
||||
Design Statistics
|
||||
# IOs : 66
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 24
|
||||
# GND : 1
|
||||
# LUT2 : 1
|
||||
# LUT3 : 2
|
||||
# LUT4 : 20
|
||||
# IO Buffers : 66
|
||||
# IBUF : 64
|
||||
# OBUF : 2
|
||||
=========================================================================
|
||||
|
||||
Device utilization summary:
|
||||
---------------------------
|
||||
|
||||
Selected Device : 3s50pq208-5
|
||||
|
||||
Number of Slices: 13 out of 768 1%
|
||||
Number of 4 input LUTs: 23 out of 1536 1%
|
||||
Number of IOs: 66
|
||||
Number of bonded IOBs: 66 out of 124 53%
|
||||
|
||||
---------------------------
|
||||
Partition Resource Summary:
|
||||
---------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
---------------------------
|
||||
|
||||
|
||||
=========================================================================
|
||||
TIMING REPORT
|
||||
|
||||
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||||
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
||||
GENERATED AFTER PLACE-and-ROUTE.
|
||||
|
||||
Clock Information:
|
||||
------------------
|
||||
No clock signals found in this design
|
||||
|
||||
Asynchronous Control Signals Information:
|
||||
----------------------------------------
|
||||
No asynchronous control signals found in this design
|
||||
|
||||
Timing Summary:
|
||||
---------------
|
||||
Speed Grade: -5
|
||||
|
||||
Minimum period: No path found
|
||||
Minimum input arrival time before clock: No path found
|
||||
Maximum output required time after clock: No path found
|
||||
Maximum combinational path delay: 13.307ns
|
||||
|
||||
Timing Detail:
|
||||
--------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default path analysis
|
||||
Total number of paths / destination ports: 72 / 1
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 13.307ns (Levels of Logic = 7)
|
||||
Source: Y<8> (PAD)
|
||||
Destination: isNan (PAD)
|
||||
|
||||
Data Path: Y<8> to isNan
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 1 0.715 0.976 Y_8_IBUF (Y_8_IBUF)
|
||||
LUT4:I0->O 1 0.479 0.976 isNan35 (isNan35)
|
||||
LUT2:I0->O 1 0.479 0.704 isNan41 (isNan41)
|
||||
LUT4:I3->O 1 0.479 0.976 isNan61 (isNan61)
|
||||
LUT3:I0->O 1 0.479 0.976 isNan209_SW0 (N6)
|
||||
LUT4:I0->O 1 0.479 0.681 isNan209 (isNan_OBUF)
|
||||
OBUF:I->O 4.909 isNan_OBUF (isNan)
|
||||
----------------------------------------
|
||||
Total 13.307ns (8.019ns logic, 5.288ns route)
|
||||
(60.3% logic, 39.7% route)
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 3.00 secs
|
||||
Total CPU time to Xst completion: 3.05 secs
|
||||
|
||||
-->
|
||||
|
||||
|
||||
Total memory usage is 584420 kilobytes
|
||||
Total memory usage is 606300 kilobytes
|
||||
|
||||
Number of errors : 5 ( 0 filtered)
|
||||
Number of warnings : 0 ( 0 filtered)
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 1 ( 0 filtered)
|
||||
Number of infos : 0 ( 0 filtered)
|
||||
|
||||
+29
-45
@@ -1,59 +1,43 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity TypeCheck is
|
||||
entity SpecialCasesCheck is
|
||||
port(
|
||||
X, Y: in std_logic_vector(31 downto 0);
|
||||
isNan, isZero: out std_logic
|
||||
);
|
||||
end SpecialCasesCheck;
|
||||
|
||||
|
||||
architecture SpecialCasesCheckArch of SpecialCasesCheck is
|
||||
component TypeCheck is
|
||||
port(
|
||||
N: in std_logic_vector(31 downto 0);
|
||||
NaN, INF: out std_logic
|
||||
);
|
||||
end TypeCheck;
|
||||
end component;
|
||||
|
||||
signal xNan: std_logic;
|
||||
signal xInf: std_logic;
|
||||
signal xSign: std_logic;
|
||||
signal yNan: std_logic;
|
||||
signal yInf: std_logic;
|
||||
signal ySign: std_logic;
|
||||
signal isSameAbsValue: std_logic;
|
||||
|
||||
architecture TypeCheckArch of TypeCheck is
|
||||
signal G_Bus: std_logic_vector(7 downto 0);
|
||||
signal T_Bus: std_logic_vector(22 downto 0);
|
||||
signal G: std_logic := '1';
|
||||
signal T: std_logic := '0';
|
||||
begin
|
||||
G_Bus <= N(30 downto 23);
|
||||
T_Bus <= N(22 downto 0);
|
||||
xCheck: TypeCheck
|
||||
port map (N => X, NaN => xNan, INF => xInf);
|
||||
yCheck: TypeCheck
|
||||
port map (N => Y, NaN => yNan, INF => yInf);
|
||||
|
||||
G_compute: process (G_Bus)
|
||||
variable G_tmp: std_logic;
|
||||
begin
|
||||
G_tmp := '1';
|
||||
for i in G_Bus'range loop
|
||||
G_tmp := G_tmp and G_Bus(i);
|
||||
end loop;
|
||||
G <= G_tmp;
|
||||
end process;
|
||||
xSign <= X(31);
|
||||
ySign <= Y(31);
|
||||
|
||||
T_compute: process (T_Bus)
|
||||
variable T_tmp: std_logic;
|
||||
begin
|
||||
T_tmp := '0';
|
||||
for i in T_Bus'range loop
|
||||
T_tmp := T_tmp or T_Bus(i);
|
||||
end loop;
|
||||
T <= T_tmp;
|
||||
end process;
|
||||
isSameAbsValue <= '0'; -- TODO
|
||||
|
||||
NaN <= G and T;
|
||||
INF <= G and (not T);
|
||||
end TypeCheckArch;
|
||||
isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign);
|
||||
isZero <= (xSign and (not ySign) and isSameAbsValue) or ((not xSign) and ySign and isSameAbsValue);
|
||||
end SpecialCasesCheckArch;
|
||||
|
||||
|
||||
|
||||
--entity SpecialCasesCheck is
|
||||
-- port(
|
||||
-- X, Y: in std_logic_vector(31 downto 0);
|
||||
-- isNan, isZero: out std_logic
|
||||
-- );
|
||||
--end SpecialCasesCheck;
|
||||
--
|
||||
--
|
||||
--architecture SpecialCasesCheckArch of SpecialCasesCheck is
|
||||
--
|
||||
--begin
|
||||
--
|
||||
--end SpecialCasesCheckArch;
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Sat Aug 17 16:39:00 2019">
|
||||
<application stringID="Xst" timeStamp="Sat Aug 17 18:43:52 2019">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@@ -117,9 +117,50 @@
|
||||
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
|
||||
<item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
|
||||
<section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REPORT">
|
||||
<section stringID="XST_FINAL_RESULTS">
|
||||
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck.ngr"/>
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck"/>
|
||||
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
|
||||
<item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
|
||||
<item stringID="XST_KEEP_HIERARCHY" value="No"/>
|
||||
</section>
|
||||
<section stringID="XST_DESIGN_STATISTICS">
|
||||
<item stringID="XST_IOS" value="66"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="24">
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT2" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="2"/>
|
||||
<item dataType="int" stringID="XST_LUT4" value="20"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="66">
|
||||
<item dataType="int" stringID="XST_IBUF" value="64"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="2"/>
|
||||
</item>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
|
||||
<item stringID="XST_SELECTED_DEVICE" value="3s50pq208-5"/>
|
||||
<item AVAILABLE="768" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="13"/>
|
||||
<item AVAILABLE="1536" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="23"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="66"/>
|
||||
<item AVAILABLE="124" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="5"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="1"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
@@ -0,0 +1,43 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity TypeCheck is
|
||||
port(
|
||||
N: in std_logic_vector(31 downto 0);
|
||||
NaN, INF: out std_logic
|
||||
);
|
||||
end TypeCheck;
|
||||
|
||||
architecture TypeCheckArch of TypeCheck is
|
||||
signal G_Bus: std_logic_vector(7 downto 0);
|
||||
signal T_Bus: std_logic_vector(22 downto 0);
|
||||
signal G: std_logic := '1';
|
||||
signal T: std_logic := '0';
|
||||
begin
|
||||
G_Bus <= N(30 downto 23);
|
||||
T_Bus <= N(22 downto 0);
|
||||
|
||||
G_compute: process (G_Bus)
|
||||
variable G_tmp: std_logic;
|
||||
begin
|
||||
G_tmp := '1';
|
||||
for i in G_Bus'range loop
|
||||
G_tmp := G_tmp and G_Bus(i);
|
||||
end loop;
|
||||
G <= G_tmp;
|
||||
end process;
|
||||
|
||||
T_compute: process (T_Bus)
|
||||
variable T_tmp: std_logic;
|
||||
begin
|
||||
T_tmp := '0';
|
||||
for i in T_Bus'range loop
|
||||
T_tmp := T_tmp or T_Bus(i);
|
||||
end loop;
|
||||
T <= T_tmp;
|
||||
end process;
|
||||
|
||||
NaN <= G and T;
|
||||
INF <= G and (not T);
|
||||
end TypeCheckArch;
|
||||
|
||||
+12
-19
@@ -3,44 +3,37 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Sat Aug 17 17:02:15 2019">
|
||||
<application name="pn" timeStamp="Sat Aug 17 18:43:50 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="144FE553FD2E31FF5236C06C33BACBB5" type="project"/>
|
||||
<property name="ProjectIteration" value="2" type="project"/>
|
||||
<property name="ProjectID" value="0" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
<property name="ProjectFile" value="/home/Luca/ISE/IEEE754Adder/IEEE754Adder.xise" type="project"/>
|
||||
<property name="ProjectCreationTimestamp" value="2019-08-17T15:21:55" type="project"/>
|
||||
<property name="ProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="project"/>
|
||||
</section>
|
||||
<section name="Project Statistics" visible="true">
|
||||
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
|
||||
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
|
||||
<property name="PROP_LastAppliedGoal" value="Minimum Runtime" type="design"/>
|
||||
<property name="PROP_LastAppliedStrategy" value="Runtime Strategy 1;/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" type="design"/>
|
||||
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
|
||||
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
|
||||
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
|
||||
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
|
||||
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
|
||||
<property name="PROP_SynthTopFile" value="changed" type="process"/>
|
||||
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
|
||||
<property name="PROP_UseSmartGuide" value="false" type="design"/>
|
||||
<property name="PROP_UserBrowsedStrategyFiles" value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" type="process"/>
|
||||
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
|
||||
<property name="PROP_intProjectCreationTimestamp" value="2019-08-17T15:21:55" type="design"/>
|
||||
<property name="PROP_intWbtProjectID" value="144FE553FD2E31FF5236C06C33BACBB5" type="design"/>
|
||||
<property name="PROP_intWbtProjectIteration" value="2" type="process"/>
|
||||
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
|
||||
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
|
||||
<property name="PROP_xilxPARplacerEffortLevel" value="Standard" type="process"/>
|
||||
<property name="PROP_xilxPARrouterEffortLevel" value="Standard" type="process"/>
|
||||
<property name="PROP_UserBrowsedStrategyFiles" value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" type="process"/>
|
||||
<property name="PROP_intProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="design"/>
|
||||
<property name="PROP_intWbtProjectID" value="0" type="design"/>
|
||||
<property name="PROP_intWorkingDirLocWRTProjDir" value="UnableToCalculate" type="design"/>
|
||||
<property name="PROP_intWorkingDirUsed" value="Unknown" type="design"/>
|
||||
<property name="PROP_AutoTop" value="true" type="design"/>
|
||||
<property name="PROP_DevFamily" value="Spartan3" type="design"/>
|
||||
<property name="PROP_MapEffortLevel" value="Standard" type="process"/>
|
||||
<property name="PROP_xilxPAReffortLevel" value="Standard" type="process"/>
|
||||
<property name="PROP_DevDevice" value="xc3s50" type="design"/>
|
||||
<property name="PROP_DevFamilyPMName" value="spartan3" type="design"/>
|
||||
<property name="PROP_DevPackage" value="pq208" type="design"/>
|
||||
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
|
||||
<property name="PROP_DevSpeed" value="-5" type="design"/>
|
||||
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
|
||||
<property name="FILE_VHDL" value="1" type="source"/>
|
||||
<property name="FILE_VHDL" value="2" type="source"/>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
+4
-2
@@ -1,2 +1,4 @@
|
||||
EN typecheck NULL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd sub00/vhpl00 1566054138
|
||||
AR typecheck typecheckarch /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd sub00/vhpl01 1566054139
|
||||
AR specialcasescheck specialcasescheckarch /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd sub00/vhpl03 1566060236
|
||||
EN typecheck NULL /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd sub00/vhpl00 1566060233
|
||||
AR typecheck typecheckarch /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd sub00/vhpl01 1566060234
|
||||
EN specialcasescheck NULL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd sub00/vhpl02 1566060235
|
||||
+11
-5
@@ -1,6 +1,12 @@
|
||||
V3 3
|
||||
FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd 2019/08/17.16:59:45 P.20131013
|
||||
EN work/TypeCheck 1566054138 FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd \
|
||||
V3 7
|
||||
FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd 2019/08/17.18:43:39 P.20131013
|
||||
EN work/SpecialCasesCheck 1566060235 \
|
||||
FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd PB ieee/std_logic_1164 1381692176
|
||||
AR work/SpecialCasesCheck/SpecialCasesCheckArch 1566060236 \
|
||||
FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd \
|
||||
EN work/SpecialCasesCheck 1566060235 CP TypeCheck
|
||||
FL /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd 2019/08/17.18:42:06 P.20131013
|
||||
EN work/TypeCheck 1566060233 FL /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd \
|
||||
PB ieee/std_logic_1164 1381692176
|
||||
AR work/TypeCheck/TypeCheckArch 1566054139 \
|
||||
FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd EN work/TypeCheck 1566054138
|
||||
AR work/TypeCheck/TypeCheckArch 1566060234 \
|
||||
FL /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd EN work/TypeCheck 1566060233
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Reference in new issue
Block a user