lucacuzzocrea/IEEE754Adder
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Aggiunto controllo risultato NaN

Browse Source
This commit is contained in:
Luca Cuzzocrea
2019-08-17 18:45:31 +02:00
parent a1b9650580
commit 47cc74e0d0
18 changed files with 380 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
IEEE754Adder.gise
View File

@@ -24,7 +24,10 @@
<files xmlns="http://www.xilinx.com/XMLSchema"> <files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SpecialCasesCheck.cmd_log"/> <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SpecialCasesCheck.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SpecialCasesCheck.lso"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SpecialCasesCheck.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SpecialCasesCheck.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SpecialCasesCheck.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesCheck.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesCheck.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SpecialCasesCheck.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SpecialCasesCheck.syr"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SpecialCasesCheck.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SpecialCasesCheck.xst"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SpecialCasesCheck.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="SpecialCasesCheck_envsettings.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="SpecialCasesCheck_envsettings.html"/>
@@ -83,11 +86,11 @@
<transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1566052458"> <transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1566052458">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1566052805" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3534754566125264796" xil_pn:start_ts="1566052805"> <transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1167941000477774584" xil_pn:start_ts="1566059978">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1566052805" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8013279211492191508" xil_pn:start_ts="1566052805"> <transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8700953375414271688" xil_pn:start_ts="1566059978">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
@@ -95,7 +98,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1566052805" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1039519274070425884" xil_pn:start_ts="1566052805"> <transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2391194399288376768" xil_pn:start_ts="1566059978">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
@@ -103,21 +106,22 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1566052805" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4325541895085471050" xil_pn:start_ts="1566052805"> <transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1647368633314702702" xil_pn:start_ts="1566059978">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1566054140" xil_pn:in_ck="-4395428264884964098" xil_pn:name="TRANEXT_xstsynthesize_spartan3" xil_pn:prop_ck="2853843150675393866" xil_pn:start_ts="1566054134"> <transform xil_pn:end_ts="1566060235" xil_pn:in_ck="-3235492353642026610" xil_pn:name="TRANEXT_xstsynthesize_spartan3" xil_pn:prop_ck="-5588158190480725594" xil_pn:start_ts="1566060230">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="TypeCheck.lso"/> <outfile xil_pn:name="SpecialCasesCheck.lso"/>
<outfile xil_pn:name="TypeCheck.ngc"/> <outfile xil_pn:name="SpecialCasesCheck.ngc"/>
<outfile xil_pn:name="SpecialCasesCheck.ngr"/>
<outfile xil_pn:name="SpecialCasesCheck.prj"/>
<outfile xil_pn:name="SpecialCasesCheck.stx"/>
<outfile xil_pn:name="SpecialCasesCheck.syr"/>
<outfile xil_pn:name="SpecialCasesCheck.xst"/>
<outfile xil_pn:name="SpecialCasesCheck_xst.xrpt"/>
<outfile xil_pn:name="TypeCheck.ngr"/> <outfile xil_pn:name="TypeCheck.ngr"/>
<outfile xil_pn:name="TypeCheck.prj"/>
<outfile xil_pn:name="TypeCheck.stx"/>
<outfile xil_pn:name="TypeCheck.syr"/>
<outfile xil_pn:name="TypeCheck.xst"/>
<outfile xil_pn:name="TypeCheck_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
@@ -125,11 +129,15 @@
<transform xil_pn:end_ts="1566052811" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-2497314214044977511" xil_pn:start_ts="1566052811"> <transform xil_pn:end_ts="1566052811" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-2497314214044977511" xil_pn:start_ts="1566052811">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform> </transform>
<transform xil_pn:end_ts="1566052856" xil_pn:in_ck="-1179315243053685338" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7709254264864982892" xil_pn:start_ts="1566052852"> <transform xil_pn:end_ts="1566052856" xil_pn:in_ck="-1179315243053685338" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7709254264864982892" xil_pn:start_ts="1566052852">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="TypeCheck.bld"/> <outfile xil_pn:name="TypeCheck.bld"/>
<outfile xil_pn:name="TypeCheck.ngd"/> <outfile xil_pn:name="TypeCheck.ngd"/>

21
IEEE754Adder.xise
View File

@@ -17,6 +17,10 @@
<files> <files>
<file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
</files> </files>
@@ -142,8 +146,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|TypeCheck|TypeCheckArch" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SpecialCasesCheck|SpecialCasesCheckArch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="SpecialCasesCheck.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SpecialCasesCheck" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -207,7 +212,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="TypeCheck" xil_pn:valueState="default"/> <property xil_pn:name="Output File Name" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -222,10 +227,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="TypeCheck_map.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SpecialCasesCheck_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="TypeCheck_timesim.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="SpecialCasesCheck_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="TypeCheck_synthesis.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SpecialCasesCheck_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="TypeCheck_translate.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SpecialCasesCheck_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -251,7 +256,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="TypeCheck" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

3
SpecialCasesCheck.cmd_log
View File

@@ -2,3 +2,6 @@ xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"

3
SpecialCasesCheck.ngc Normal file
View File

File diff suppressed because one or more lines are too long

3
SpecialCasesCheck.ngr Normal file
View File

File diff suppressed because one or more lines are too long

1
SpecialCasesCheck.prj
View File

@@ -1 +1,2 @@
vhdl work "TypeCheck.vhd"
vhdl work "SpecialCasesCheck.vhd" vhdl work "SpecialCasesCheck.vhd"

0
SpecialCasesCheck.stx Normal file
View File

203
SpecialCasesCheck.syr
View File

@@ -5,14 +5,14 @@ Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs Total CPU time to Xst completion: 0.05 secs
--> -->
Parameter xsthdpdir set to xst Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs Total CPU time to Xst completion: 0.05 secs
--> -->
Reading design: SpecialCasesCheck.prj Reading design: SpecialCasesCheck.prj
@@ -107,20 +107,199 @@ Slice Utilization Ratio Delta : 5
========================================================================= =========================================================================
* HDL Compilation * * HDL Compilation *
========================================================================= =========================================================================
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" in Library work.
Architecture typecheckarch of Entity typecheck is up to date.
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work. Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work.
Entity <typecheck> compiled. Entity <specialcasescheck> compiled.
Entity <typecheck> (Architecture <typecheckarch>) compiled. Entity <specialcasescheck> (Architecture <specialcasescheckarch>) compiled.
ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. Undefined symbol 'std_logic_vector'.
ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. std_logic_vector: Undefined symbol (last report in this block) =========================================================================
ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. Undefined symbol 'std_logic'. * Design Hierarchy Analysis *
ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. std_logic: Undefined symbol (last report in this block) =========================================================================
ERROR:HDLParsers:3010 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 55. Entity SpecialCasesCheck does not exist. Analyzing hierarchy for entity <SpecialCasesCheck> in library <work> (architecture <specialcasescheckarch>).
Analyzing hierarchy for entity <TypeCheck> in library <work> (architecture <typecheckarch>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <SpecialCasesCheck> in library <work> (Architecture <specialcasescheckarch>).
Entity <SpecialCasesCheck> analyzed. Unit <SpecialCasesCheck> generated.
Analyzing Entity <TypeCheck> in library <work> (Architecture <typecheckarch>).
Entity <TypeCheck> analyzed. Unit <TypeCheck> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <TypeCheck>.
Related source file is "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd".
WARNING:Xst:647 - Input <N<31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <TypeCheck> synthesized.
Synthesizing Unit <SpecialCasesCheck>.
Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd".
Unit <SpecialCasesCheck> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <SpecialCasesCheck> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 1.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : SpecialCasesCheck.ngr
Top Level Output File Name : SpecialCasesCheck
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 66
Cell Usage :
# BELS : 24
# GND : 1
# LUT2 : 1
# LUT3 : 2
# LUT4 : 20
# IO Buffers : 66
# IBUF : 64
# OBUF : 2
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s50pq208-5
Number of Slices: 13 out of 768 1%
Number of 4 input LUTs: 23 out of 1536 1%
Number of IOs: 66
Number of bonded IOBs: 66 out of 124 53%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 13.307ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 72 / 1
-------------------------------------------------------------------------
Delay: 13.307ns (Levels of Logic = 7)
Source: Y<8> (PAD)
Destination: isNan (PAD)
Data Path: Y<8> to isNan
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.715 0.976 Y_8_IBUF (Y_8_IBUF)
LUT4:I0->O 1 0.479 0.976 isNan35 (isNan35)
LUT2:I0->O 1 0.479 0.704 isNan41 (isNan41)
LUT4:I3->O 1 0.479 0.976 isNan61 (isNan61)
LUT3:I0->O 1 0.479 0.976 isNan209_SW0 (N6)
LUT4:I0->O 1 0.479 0.681 isNan209 (isNan_OBUF)
OBUF:I->O 4.909 isNan_OBUF (isNan)
----------------------------------------
Total 13.307ns (8.019ns logic, 5.288ns route)
(60.3% logic, 39.7% route)
=========================================================================
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.05 secs
--> -->
Total memory usage is 584420 kilobytes Total memory usage is 606300 kilobytes
Number of errors : 5 ( 0 filtered) Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)

78
SpecialCasesCheck.vhd
View File

@@ -1,59 +1,43 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity TypeCheck is entity SpecialCasesCheck is
port( port(
N: in std_logic_vector(31 downto 0); X, Y: in std_logic_vector(31 downto 0);
NaN, INF: out std_logic isNan, isZero: out std_logic
); );
end TypeCheck; end SpecialCasesCheck;
architecture SpecialCasesCheckArch of SpecialCasesCheck is
component TypeCheck is
port(
N: in std_logic_vector(31 downto 0);
NaN, INF: out std_logic
);
end component;
signal xNan: std_logic;
signal xInf: std_logic;
signal xSign: std_logic;
signal yNan: std_logic;
signal yInf: std_logic;
signal ySign: std_logic;
signal isSameAbsValue: std_logic;
architecture TypeCheckArch of TypeCheck is
signal G_Bus: std_logic_vector(7 downto 0);
signal T_Bus: std_logic_vector(22 downto 0);
signal G: std_logic := '1';
signal T: std_logic := '0';
begin begin
G_Bus <= N(30 downto 23); xCheck: TypeCheck
T_Bus <= N(22 downto 0); port map (N => X, NaN => xNan, INF => xInf);
yCheck: TypeCheck
port map (N => Y, NaN => yNan, INF => yInf);
G_compute: process (G_Bus) xSign <= X(31);
variable G_tmp: std_logic; ySign <= Y(31);
begin
G_tmp := '1';
for i in G_Bus'range loop
G_tmp := G_tmp and G_Bus(i);
end loop;
G <= G_tmp;
end process;
T_compute: process (T_Bus) isSameAbsValue <= '0'; -- TODO
variable T_tmp: std_logic;
begin
T_tmp := '0';
for i in T_Bus'range loop
T_tmp := T_tmp or T_Bus(i);
end loop;
T <= T_tmp;
end process;
NaN <= G and T; isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign);
INF <= G and (not T); isZero <= (xSign and (not ySign) and isSameAbsValue) or ((not xSign) and ySign and isSameAbsValue);
end TypeCheckArch; end SpecialCasesCheckArch;
--entity SpecialCasesCheck is
-- port(
-- X, Y: in std_logic_vector(31 downto 0);
-- isNan, isZero: out std_logic
-- );
--end SpecialCasesCheck;
--
--
--architecture SpecialCasesCheckArch of SpecialCasesCheck is
--
--begin
--
--end SpecialCasesCheckArch;

47
SpecialCasesCheck_xst.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sat Aug 17 16:39:00 2019"> <application stringID="Xst" timeStamp="Sat Aug 17 18:43:52 2019">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
@@ -117,9 +117,50 @@
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/> <item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
<item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/> <item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
</section> </section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
<section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
</section>
<section stringID="XST_FINAL_REPORT">
<section stringID="XST_FINAL_RESULTS">
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck.ngr"/>
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck"/>
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
<item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
<item stringID="XST_KEEP_HIERARCHY" value="No"/>
</section>
<section stringID="XST_DESIGN_STATISTICS">
<item stringID="XST_IOS" value="66"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="24">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_LUT2" value="1"/>
<item dataType="int" stringID="XST_LUT3" value="2"/>
<item dataType="int" stringID="XST_LUT4" value="20"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="66">
<item dataType="int" stringID="XST_IBUF" value="64"/>
<item dataType="int" stringID="XST_OBUF" value="2"/>
</item>
</section>
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="3s50pq208-5"/>
<item AVAILABLE="768" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="13"/>
<item AVAILABLE="1536" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="23"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="66"/>
<item AVAILABLE="124" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
<section stringID="XST_ERRORS_STATISTICS"> <section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="5"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="1"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
</section> </section>
</application> </application>

43
TypeCheck.vhd Normal file
View File

@@ -0,0 +1,43 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TypeCheck is
port(
N: in std_logic_vector(31 downto 0);
NaN, INF: out std_logic
);
end TypeCheck;
architecture TypeCheckArch of TypeCheck is
signal G_Bus: std_logic_vector(7 downto 0);
signal T_Bus: std_logic_vector(22 downto 0);
signal G: std_logic := '1';
signal T: std_logic := '0';
begin
G_Bus <= N(30 downto 23);
T_Bus <= N(22 downto 0);
G_compute: process (G_Bus)
variable G_tmp: std_logic;
begin
G_tmp := '1';
for i in G_Bus'range loop
G_tmp := G_tmp and G_Bus(i);
end loop;
G <= G_tmp;
end process;
T_compute: process (T_Bus)
variable T_tmp: std_logic;
begin
T_tmp := '0';
for i in T_Bus'range loop
T_tmp := T_tmp or T_Bus(i);
end loop;
T <= T_tmp;
end process;
NaN <= G and T;
INF <= G and (not T);
end TypeCheckArch;

31
webtalk_pn.xml
View File

@@ -3,44 +3,37 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Aug 17 17:02:15 2019"> <application name="pn" timeStamp="Sat Aug 17 18:43:50 2019">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="144FE553FD2E31FF5236C06C33BACBB5" type="project"/> <property name="ProjectID" value="0" type="project"/>
<property name="ProjectIteration" value="2" type="project"/> <property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="/home/Luca/ISE/IEEE754Adder/IEEE754Adder.xise" type="project"/> <property name="ProjectFile" value="/home/Luca/ISE/IEEE754Adder/IEEE754Adder.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2019-08-17T15:21:55" type="project"/> <property name="ProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="project"/>
</section> </section>
<section name="Project Statistics" visible="true"> <section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/> <property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/> <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedGoal" value="Minimum Runtime" type="design"/> <property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Runtime Strategy 1;/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/> <property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/> <property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/> <property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/> <property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/> <property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/> <property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserBrowsedStrategyFiles" value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" type="process"/> <property name="PROP_UserBrowsedStrategyFiles" value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" type="process"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_intProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="design"/>
<property name="PROP_intProjectCreationTimestamp" value="2019-08-17T15:21:55" type="design"/> <property name="PROP_intWbtProjectID" value="0" type="design"/>
<property name="PROP_intWbtProjectID" value="144FE553FD2E31FF5236C06C33BACBB5" type="design"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="UnableToCalculate" type="design"/>
<property name="PROP_intWbtProjectIteration" value="2" type="process"/> <property name="PROP_intWorkingDirUsed" value="Unknown" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_xilxPARplacerEffortLevel" value="Standard" type="process"/>
<property name="PROP_xilxPARrouterEffortLevel" value="Standard" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/> <property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="Spartan3" type="design"/> <property name="PROP_DevFamily" value="Spartan3" type="design"/>
<property name="PROP_MapEffortLevel" value="Standard" type="process"/>
<property name="PROP_xilxPAReffortLevel" value="Standard" type="process"/>
<property name="PROP_DevDevice" value="xc3s50" type="design"/> <property name="PROP_DevDevice" value="xc3s50" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3" type="design"/> <property name="PROP_DevFamilyPMName" value="spartan3" type="design"/>
<property name="PROP_DevPackage" value="pq208" type="design"/> <property name="PROP_DevPackage" value="pq208" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-5" type="design"/> <property name="PROP_DevSpeed" value="-5" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/> <property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="1" type="source"/> <property name="FILE_VHDL" value="2" type="source"/>
</section> </section>
</application> </application>
</document> </document>

6
xst/work/hdllib.ref
View File

@@ -1,2 +1,4 @@
EN typecheck NULL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd sub00/vhpl00 1566054138 AR specialcasescheck specialcasescheckarch /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd sub00/vhpl03 1566060236
AR typecheck typecheckarch /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd sub00/vhpl01 1566054139 EN typecheck NULL /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd sub00/vhpl00 1566060233
AR typecheck typecheckarch /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd sub00/vhpl01 1566060234
EN specialcasescheck NULL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd sub00/vhpl02 1566060235

16
xst/work/hdpdeps.ref
View File

@@ -1,6 +1,12 @@
V3 3 V3 7
FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd 2019/08/17.16:59:45 P.20131013 FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd 2019/08/17.18:43:39 P.20131013
EN work/TypeCheck 1566054138 FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd \ EN work/SpecialCasesCheck 1566060235 \
FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd PB ieee/std_logic_1164 1381692176
AR work/SpecialCasesCheck/SpecialCasesCheckArch 1566060236 \
FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd \
EN work/SpecialCasesCheck 1566060235 CP TypeCheck
FL /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd 2019/08/17.18:42:06 P.20131013
EN work/TypeCheck 1566060233 FL /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd \
PB ieee/std_logic_1164 1381692176 PB ieee/std_logic_1164 1381692176
AR work/TypeCheck/TypeCheckArch 1566054139 \ AR work/TypeCheck/TypeCheckArch 1566060234 \
FL /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd EN work/TypeCheck 1566054138 FL /home/Luca/ISE/IEEE754Adder/TypeCheck.vhd EN work/TypeCheck 1566060233

BIN
xst/work/sub00/vhpl00.vho
View File

Binary file not shown.

BIN
xst/work/sub00/vhpl01.vho
View File

Binary file not shown.

BIN
xst/work/sub00/vhpl02.vho Normal file
View File

Binary file not shown.

BIN
xst/work/sub00/vhpl03.vho Normal file
View File

Binary file not shown.