Aggiunti test
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22
fuse.log
22
fuse.log
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj work.TwoComplementTest
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj work.SumDataAdapterTest
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ISim P.20160913 (signature 0xfbc00daa)
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Number of CPUs detected in this system: 1
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Turning on mult-threading, number of parallel sub-compilation jobs: 0
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Determining compilation order of HDL files
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplement.vhd" into library work
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplementTest.vhd" into library work
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/ShiftRight.vhd" into library work
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapter.vhd" into library work
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" into library work
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Starting static elaboration
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Completed static elaboration
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Fuse Memory Usage: 95308 KB
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Fuse CPU Usage: 2300 ms
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Compiling package standard
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Compiling package std_logic_1164
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Compiling architecture twocomplementarch of entity TwoComplement [\TwoComplement(8)\]
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Compiling architecture behavior of entity twocomplementtest
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Time Resolution for simulation is 1ps.
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Compiled 5 VHDL Units
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Built simulation executable /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe
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Fuse Memory Usage: 103960 KB
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Fuse CPU Usage: 2400 ms
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GCC CPU Usage: 1480 ms
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ERROR:HDLCompiler:410 - "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has 30 elements ; expected 31
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ERROR:Simulator:777 - Static elaboration of top level VHDL design unit sumdataadaptertest in library work failed
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