Aggiunti test

SwapTest.vhd

@@ -1,10 +1,6 @@
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
+
 ENTITY SwapTest IS
 END SwapTest;
  
@@ -24,16 +20,14 @@ ARCHITECTURE behavior OF SwapTest IS
     
 
    --Inputs
-   signal X_IN : std_logic_vector(7 downto 0) := "01010101";
-   signal Y_IN : std_logic_vector(7 downto 0) := "10101010";
-   signal SW : std_logic := '1';
+   signal X_IN : std_logic_vector(7 downto 0) := (others => '0');
+   signal Y_IN : std_logic_vector(7 downto 0) := (others => '0');
+   signal SW : std_logic := '0';
 
  	--Outputs
    signal X_OUT : std_logic_vector(7 downto 0);
    signal Y_OUT : std_logic_vector(7 downto 0);
 	signal clock : std_logic;
-   -- No clocks detected in port list. Replace clock below with 
-   -- appropriate port name 
  
    constant clock_period : time := 10 ns;
  
@@ -58,17 +52,40 @@ BEGIN
    end process;
  
 
-   -- Stimulus process
-   stim_proc: process
-   begin		
-      -- hold reset state for 100 ns.
-      wait for 100 ns;	
-
-      wait for clock_period*10;
-
-      -- insert stimulus here 
-
-      wait;
-   end process;
+	test_proc: process
+   begin
+		X_IN <= "00110000";
+		Y_IN <= "00010000";
+		SW <= '0';
+      wait for clock_period;
+		X_IN <= "01100000";
+		Y_IN <= "01110000";
+		SW <= '1';
+      wait for clock_period;
+		X_IN <= "01101000";
+		Y_IN <= "00110110";
+		SW <= '1';
+      wait for clock_period;
+		X_IN <= "00111111";
+		Y_IN <= "01000000";
+		SW <= '0';
+      wait for clock_period;
+		X_IN <= "00101001";
+		Y_IN <= "00101000";
+		SW <= '1';
+      wait for clock_period;
+		X_IN <= "00000000";
+		Y_IN <= "00000000";
+		SW <= '1';
+      wait for clock_period;
+		X_IN <= "00110000";
+		Y_IN <= "00110000";
+		SW <= '0';
+      wait for clock_period;
+		X_IN <= "11111111";
+		Y_IN <= "00000000";
+		SW <= '1';
+      wait for clock_period;
+	end process;
 
 END;