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Giulio
2019-08-30 19:24:54 +02:00
parent d077d1fe84
commit 0250f39c47
24 changed files with 565 additions and 189 deletions
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11
SumDataAdapter.vhd
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@@ -15,6 +15,8 @@ architecture SumDataAdapterArch of SumDataAdapter is
signal X_FST_BIT : std_logic;
signal Y_FST_BIT : std_logic;
signal FILL : std_logic_vector(23 downto 0);
signal N : std_logic_vector(47 downto 0);
component ShiftRight48 is
@@ -28,6 +30,8 @@ architecture SumDataAdapterArch of SumDataAdapter is
begin
FILL <= (others => '0');
X_Y_FST_BIT_PROCESS : process (X_IN, Y_IN)
variable X_FST_TMP : std_logic := '0';
@@ -45,11 +49,12 @@ begin
end process;
--istanziare shifter
N <= Y_FST_BIT & Y_IN(22 downto 0) & FILL;
SHIFTER : ShiftRight48
port map (N -> Y_FST_BIT & Y_IN(22 downto 0) & "000000000000000000000000", PLACES -> DIFF_EXP, RESULT -> Y_OUT);
port map (N => N, PLACES => DIFF_EXP, RESULT => Y_OUT);
X_OUT <= X_FST_BIT & X_IN(22 downto 0) & "000000000000000000000000";
--X_OUT <= X_FST_BIT & X_IN(22 downto 0) & FILL;
end SumDataAdapterArch;