Aggiunti test

AdderTest.vhd

@@ -8,40 +8,38 @@ ARCHITECTURE behavior OF AdderTest IS
  
     -- Component Declaration for the Unit Under Test (UUT)
  
-    COMPONENT Adder
+    COMPONENT CarryLookAhead
     PORT(
-         X : IN  std_logic_vector(7 downto 0);
-         Y : IN  std_logic_vector(7 downto 0);
-         carry_in : IN  std_logic;
-         result : OUT  std_logic_vector(7 downto 0);
-         carry_out : OUT  std_logic
+         X : IN  std_logic_vector(47 downto 0);
+         Y : IN  std_logic_vector(47 downto 0);
+         OP : IN  std_logic;
+         RESULT : OUT  std_logic_vector(47 downto 0);
+         OVERFLOW : OUT  std_logic
         );
     END COMPONENT;
     
 
    --Inputs
-   signal X : std_logic_vector(7 downto 0) := (others => '0');
-   signal Y : std_logic_vector(7 downto 0) := (others => '0');
-   signal carry_in : std_logic := '0';
+   signal X : std_logic_vector(47 downto 0) := (others => '0');
+   signal Y : std_logic_vector(47 downto 0) := (others => '0');
+   signal OP : std_logic := '0';
 
  	--Outputs
-   signal result : std_logic_vector(7 downto 0);
-   signal carry_out : std_logic;
-   -- No clocks detected in port list. Replace clock below with 
-   -- appropriate port name 
-	signal clock: std_logic;
+   signal RESULT : std_logic_vector(47 downto 0);
+   signal OVERFLOW : std_logic;
+   signal clock : std_logic;
  
    constant clock_period : time := 10 ns;
  
 BEGIN
  
 	-- Instantiate the Unit Under Test (UUT)
-   uut: Adder PORT MAP (
+   uut: CarryLookAhead PORT MAP (
           X => X,
           Y => Y,
-          carry_in => carry_in,
-          result => result,
-          carry_out => carry_out
+          OP => OP,
+          RESULT => RESULT,
+          OVERFLOW => OVERFLOW
         );
 
    -- Clock process definitions
@@ -52,8 +50,11 @@ BEGIN
 		clock <= '1';
 		wait for clock_period/2;
    end process;
- 
-	x <= "00010101";
-	y <= "00001110";
+
+	test_proc: process
+   begin
+		--test
+      wait for clock_period;
+	end process;
 
 END;