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Aggiunti test

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This commit is contained in:
Giulio
2019-08-30 19:24:54 +02:00
parent d077d1fe84
commit 0250f39c47
24 changed files with 565 additions and 189 deletions
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52
AddSubTest.vhd
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@@ -13,9 +13,9 @@ ARCHITECTURE behavior OF AddSubTest IS
PORT(
X : IN std_logic_vector(7 downto 0);
Y : IN std_logic_vector(7 downto 0);
isSub : IN std_logic;
result : OUT std_logic_vector(7 downto 0);
overflow : OUT std_logic
IS_SUB : IN std_logic;
RESULT : OUT std_logic_vector(7 downto 0);
OVERFLOW : OUT std_logic
);
END COMPONENT;
@@ -23,11 +23,11 @@ ARCHITECTURE behavior OF AddSubTest IS
--Inputs
signal X : std_logic_vector(7 downto 0) := (others => '0');
signal Y : std_logic_vector(7 downto 0) := (others => '0');
signal isSub : std_logic := '0';
signal IS_SUB : std_logic := '0';
--Outputs
signal result : std_logic_vector(7 downto 0);
signal overflow : std_logic;
signal RESULT : std_logic_vector(7 downto 0);
signal OVERFLOW : std_logic;
signal clock: std_logic;
constant clock_period : time := 10 ns;
@@ -38,9 +38,9 @@ BEGIN
uut: AddSub PORT MAP (
X => X,
Y => Y,
isSub => isSub,
result => result,
overflow => overflow
IS_SUB => IS_SUB,
RESULT => RESULT,
OVERFLOW => OVERFLOW
);
-- Clock process definitions
@@ -57,70 +57,70 @@ BEGIN
begin
X <= "00110011";
Y <= "11001100";
isSub <= '0';
IS_SUB <= '0';
wait for clock_period;
X <= "10010111";
Y <= "11100011";
isSub <= '0';
IS_SUB <= '0';
wait for clock_period;
X <= "10000101";
Y <= "01111011";
isSub <= '0';
IS_SUB <= '0';
wait for clock_period;
X <= "11111111";
Y <= "11111111";
isSub <= '0';
IS_SUB <= '0';
wait for clock_period;
X <= "00101011";
Y <= "00101010";
isSub <= '0';
IS_SUB <= '0';
wait for clock_period;
X <= "11111111";
Y <= "11111111";
isSub <= '0';
IS_SUB <= '0';
wait for clock_period;
X <= "10000000";
Y <= "10000000";
isSub <= '0';
IS_SUB <= '0';
wait for clock_period;
X <= "00000000";
Y <= "11111111";
isSub <= '0';
IS_SUB <= '0';
X <= "00110011";
Y <= "11001100";
isSub <= '1';
IS_SUB <= '1';
wait for clock_period;
X <= "10010111";
Y <= "11100011";
isSub <= '1';
IS_SUB <= '1';
wait for clock_period;
X <= "10000101";
Y <= "01111011";
isSub <= '1';
IS_SUB <= '1';
wait for clock_period;
X <= "11111111";
Y <= "11111111";
isSub <= '1';
IS_SUB <= '1';
wait for clock_period;
X <= "00101011";
Y <= "00101010";
isSub <= '1';
IS_SUB <= '1';
wait for clock_period;
X <= "11111111";
Y <= "11111111";
isSub <= '1';
IS_SUB <= '1';
wait for clock_period;
X <= "10000000";
Y <= "10000000";
isSub <= '1';
IS_SUB <= '1';
wait for clock_period;
X <= "00000000";
Y <= "11111111";
isSub <= '1';
IS_SUB <= '1';
wait for clock_period;
X <= "11111111";
Y <= "00000000";
isSub <= '1';
IS_SUB <= '1';
wait for clock_period;
end process;