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Aggiunto modulo Comparator

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This commit is contained in:
Giulio
2019-08-27 11:50:27 +02:00
parent f8b3061b00
commit 019e9a5cd8
71 changed files with 1927 additions and 76 deletions
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34
Comparator.vhd Normal file
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@@ -0,0 +1,34 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Comparator is
generic( BITCOUNT: integer := 8 );
port(
xT, yT: in std_logic_vector((BITCOUNT-1) downto 0);
needSwap: out std_logic
);
end Comparator;
architecture ComparatorArch of Comparator is
signal xGTy: std_logic_vector((BITCOUNT-1) downto 0);
signal yGTx: std_logic_vector((BITCOUNT-1) downto 0);
begin
xGTy <= xT and (not yT);
yGTx <= (not xT) and yT;
needSwap_compute: process (xGTy, yGTx)
variable SW: std_logic;
variable K: std_logic;
begin
SW := '0';
K := '1';
for i in (BITCOUNT-1) downto 0 loop
SW := SW or ((not(xGTy(i)) and yGTx(i)) and K);
K := K and (not(xGTy(i) and not(yGTx(i))));
end loop;
needSwap <= SW;
end process;
end ComparatorArch;

65
ComparatorTest.vhd Normal file
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@@ -0,0 +1,65 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ComparatorTest IS
END ComparatorTest;
ARCHITECTURE behavior OF ComparatorTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Comparator
PORT(
xT : IN std_logic_vector(7 downto 0);
yT : IN std_logic_vector(7 downto 0);
needSwap : OUT std_logic
);
END COMPONENT;
--Inputs
signal xT : std_logic_vector(7 downto 0) := "11111111";
signal yT : std_logic_vector(7 downto 0) := "11111111";
--Outputs
signal needSwap : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
signal clock: std_logic;
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Comparator PORT MAP (
xT => xT,
yT => yT,
needSwap => needSwap
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
END;

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ComparatorTest_isim_beh.exe Normal file
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ComparatorTest_isim_beh.wdb Normal file
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60
IEEE754Adder.xise
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@@ -16,31 +16,41 @@
<files>
<file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
</file>
</files>
<properties>
@@ -97,7 +107,7 @@
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xa6slx4" xil_pn:valueState="default"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -161,9 +171,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SpecialCasesCheck|SpecialCasesCheckArch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="SpecialCasesCheck.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SpecialCasesCheck" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Comparator|ComparatorArch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="Comparator.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Comparator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -232,7 +242,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="Comparator" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -247,10 +257,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SpecialCasesCheck_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="SpecialCasesCheck_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SpecialCasesCheck_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SpecialCasesCheck_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Comparator_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Comparator_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Comparator_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Comparator_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -274,7 +284,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Comparator" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -298,8 +308,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SpecialCasesTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SpecialCasesTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ComparatorTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ComparatorTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -318,7 +328,7 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SpecialCasesTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ComparatorTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -373,7 +383,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|SpecialCasesTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|ComparatorTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

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SpecialCasesTest_isim_beh.wdb
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2
equalCheck.vhd
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@@ -21,7 +21,7 @@ begin
for i in compVec'range loop
res_tmp := res_tmp or compVec(i);
end loop;
isEqual <= res_tmp;
isEqual <= not res_tmp;
end process;
end EqualCheckArch;

39
fuse.log
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@@ -1,30 +1,21 @@
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_beh.prj work.SpecialCasesTest
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/ComparatorTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/ComparatorTest_beh.prj" "work.ComparatorTest"
ISim P.20160913 (signature 0xfbc00daa)
Number of CPUs detected in this system: 1
Turning on mult-threading, number of parallel sub-compilation jobs: 0
Determining compilation order of HDL files
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/Comparator.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/ComparatorTest.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 94420 KB
Fuse CPU Usage: 980 ms
Fuse Memory Usage: 95308 KB
Fuse CPU Usage: 2480 ms
Compiling package standard
Compiling package std_logic_1164
Compiling architecture typecheckarch of entity TypeCheck [typecheck_default]
Compiling architecture nancheckarch of entity NaNCheck [nancheck_default]
Compiling architecture equalcheckarch of entity EqualCheck [\EqualCheck(31)\]
Compiling architecture zerocheckarch of entity ZeroCheck [zerocheck_default]
Compiling architecture specialcasescheckarch of entity SpecialCasesCheck [specialcasescheck_default]
Compiling architecture behavior of entity specialcasestest
Compiling architecture comparatorarch of entity Comparator [\Comparator(8)\]
Compiling architecture behavior of entity comparatortest
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 13 VHDL Units
Built simulation executable /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe
Fuse Memory Usage: 658120 KB
Fuse CPU Usage: 1000 ms
GCC CPU Usage: 280 ms
Compiled 5 VHDL Units
Built simulation executable /home/ise/gianni/IEEE754Adder/ComparatorTest_isim_beh.exe
Fuse Memory Usage: 103952 KB
Fuse CPU Usage: 2590 ms
GCC CPU Usage: 360 ms

2
fuseRelaunch.cmd
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@@ -1 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest_beh.prj" "work.SpecialCasesTest"
-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/ComparatorTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/ComparatorTest_beh.prj" "work.ComparatorTest"

94
isim.log
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@@ -1,14 +1,96 @@
ISim log file
Running: /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.wdb
ISim P.20131013 (signature 0xfbc00daa)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Running: /home/ise/gianni/IEEE754Adder/ComparatorTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/ComparatorTest_isim_beh.wdb
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# exit 0

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isim/ComparatorTest_isim_beh.exe.sim/ComparatorTest_isim_beh.exe Normal file
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isim/ComparatorTest_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Normal file
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isim/ComparatorTest_isim_beh.exe.sim/isimcrash.log Normal file
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28
isim/ComparatorTest_isim_beh.exe.sim/isimkernel.log Normal file
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@@ -0,0 +1,28 @@
Command line:
ComparatorTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 40809
Tue Aug 27 09:47:36 2019
Elaboration Time: 0.12 sec
Current Memory Usage: 198.607 Meg
Total Signals : 9
Total Nets : 34
Total Signal Drivers : 4
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 5
Total Traceable Variables : 10
Total Scalar Nets and Variables : 396
Total Simulation Time: 0.13 sec
Current Memory Usage: 276.206 Meg
Tue Aug 27 09:47:41 2019

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isim/ComparatorTest_isim_beh.exe.sim/netId.dat Normal file
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isim/ComparatorTest_isim_beh.exe.sim/tmp_save/_1 Normal file
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40
isim/ComparatorTest_isim_beh.exe.sim/work/ComparatorTest_isim_beh.exe_main.c Normal file
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@@ -0,0 +1,40 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_0883098610_0495709306_init();
work_a_1038528572_2372691052_init();
xsi_register_tops("work_a_1038528572_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/Comparator.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439989832805790689_503743352(char *, char *, char *, char *, char *, char *);
char *ieee_p_2592010699_sub_207919886985903570_503743352(char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_0883098610_0495709306_p_0(char *t0)
{
char t1[16];
char t4[16];
char *t2;
char *t3;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(17, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 6144U);
t5 = (t0 + 1192U);
t6 = *((char **)t5);
t5 = (t0 + 6160U);
t7 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t4, t6, t5);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t3, t2, t7, t4);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4112);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4000);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_0883098610_0495709306_p_1(char *t0)
{
char t1[16];
char t2[16];
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t3 = (t0 + 1032U);
t4 = *((char **)t3);
t3 = (t0 + 6144U);
t5 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t2, t4, t3);
t6 = (t0 + 1192U);
t7 = *((char **)t6);
t6 = (t0 + 6160U);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t5, t2, t7, t6);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4176);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4016);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_0883098610_0495709306_p_2(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
int t5;
char *t6;
char *t7;
unsigned char t8;
char *t9;
int t10;
int t11;
unsigned int t12;
unsigned int t13;
unsigned int t14;
char *t15;
unsigned char t16;
unsigned char t17;
char *t18;
char *t19;
int t20;
int t21;
unsigned int t22;
unsigned int t23;
unsigned int t24;
char *t25;
unsigned char t26;
unsigned char t27;
char *t28;
char *t29;
unsigned char t30;
unsigned char t31;
unsigned char t32;
char *t33;
LAB0: xsi_set_current_line(24, ng0);
t1 = (t0 + 2088U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(25, ng0);
t1 = (t0 + 2208U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(26, ng0);
t3 = (8 - 1);
t1 = (t0 + 6254);
*((int *)t1) = t3;
t2 = (t0 + 6258);
*((int *)t2) = 0;
t4 = t3;
t5 = 0;
LAB2: if (t4 >= t5)
goto LAB3;
LAB5: xsi_set_current_line(30, ng0);
t1 = (t0 + 2088U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 4240);
t6 = (t1 + 56U);
t7 = *((char **)t6);
t9 = (t7 + 56U);
t15 = *((char **)t9);
*((unsigned char *)t15) = t8;
xsi_driver_first_trans_fast_port(t1);
t1 = (t0 + 4032);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(27, ng0);
t6 = (t0 + 2088U);
t7 = *((char **)t6);
t8 = *((unsigned char *)t7);
t6 = (t0 + 1512U);
t9 = *((char **)t6);
t6 = (t0 + 6254);
t10 = *((int *)t6);
t11 = (t10 - 7);
t12 = (t11 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t6));
t13 = (1U * t12);
t14 = (0 + t13);
t15 = (t9 + t14);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16);
t18 = (t0 + 1672U);
t19 = *((char **)t18);
t18 = (t0 + 6254);
t20 = *((int *)t18);
t21 = (t20 - 7);
t22 = (t21 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t18));
t23 = (1U * t22);
t24 = (0 + t23);
t25 = (t19 + t24);
t26 = *((unsigned char *)t25);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t17, t26);
t28 = (t0 + 2208U);
t29 = *((char **)t28);
t30 = *((unsigned char *)t29);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t27, t30);
t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t8, t31);
t28 = (t0 + 2088U);
t33 = *((char **)t28);
t28 = (t33 + 0);
*((unsigned char *)t28) = t32;
xsi_set_current_line(28, ng0);
t1 = (t0 + 2208U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 1512U);
t6 = *((char **)t1);
t1 = (t0 + 6254);
t3 = *((int *)t1);
t10 = (t3 - 7);
t12 = (t10 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t1));
t13 = (1U * t12);
t14 = (0 + t13);
t7 = (t6 + t14);
t16 = *((unsigned char *)t7);
t9 = (t0 + 1672U);
t15 = *((char **)t9);
t9 = (t0 + 6254);
t11 = *((int *)t9);
t20 = (t11 - 7);
t22 = (t20 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t9));
t23 = (1U * t22);
t24 = (0 + t23);
t18 = (t15 + t24);
t17 = *((unsigned char *)t18);
t26 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t17);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t16, t26);
t30 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t27);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t30);
t19 = (t0 + 2208U);
t25 = *((char **)t19);
t19 = (t25 + 0);
*((unsigned char *)t19) = t31;
LAB4: t1 = (t0 + 6254);
t4 = *((int *)t1);
t2 = (t0 + 6258);
t5 = *((int *)t2);
if (t4 == t5)
goto LAB5;
LAB6: t3 = (t4 + -1);
t4 = t3;
t6 = (t0 + 6254);
*((int *)t6) = t4;
goto LAB2;
}
extern void work_a_0883098610_0495709306_init()
{
static char *pe[] = {(void *)work_a_0883098610_0495709306_p_0,(void *)work_a_0883098610_0495709306_p_1,(void *)work_a_0883098610_0495709306_p_2};
xsi_register_didat("work_a_0883098610_0495709306", "isim/ComparatorTest_isim_beh.exe.sim/work/a_0883098610_0495709306.didat");
xsi_register_executes(pe);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/ComparatorTest.vhd";
static void work_a_1038528572_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 2784U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(45, ng0);
t2 = (t0 + 3416);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(46, ng0);
t2 = (t0 + 1808U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2592);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(47, ng0);
t2 = (t0 + 3416);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(48, ng0);
t2 = (t0 + 1808U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2592);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_1038528572_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
LAB0: t1 = (t0 + 3032U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(56, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 2840);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(58, ng0);
t2 = (t0 + 1808U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 2840);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(62, ng0);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: goto LAB2;
LAB13: goto LAB12;
LAB15: goto LAB13;
}
extern void work_a_1038528572_2372691052_init()
{
static char *pe[] = {(void *)work_a_1038528572_2372691052_p_0,(void *)work_a_1038528572_2372691052_p_1};
xsi_register_didat("work_a_1038528572_2372691052", "isim/ComparatorTest_isim_beh.exe.sim/work/a_1038528572_2372691052.didat");
xsi_register_executes(pe);
}

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<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1000 ms, 658120 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>2590 ms, 103952 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>48</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>239</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>8</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>26</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>9</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>34</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>5</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.04 sec, 271904 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.13 sec, 275152 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>

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Command line:
pr_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 53338
Tue Aug 27 08:37:19 2019
Elaboration Time: 0.13 sec
Current Memory Usage: 198.603 Meg
Total Signals : 7
Total Nets : 49
Total Signal Drivers : 5
Total Blocks : 2
Total Primitive Blocks : 2
Total Processes : 5
Total Traceable Variables : 9
Total Scalar Nets and Variables : 410
Total Simulation Time: 0.14 sec
Current Memory Usage: 276.201 Meg
Tue Aug 27 08:37:30 2019

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isim/pr_isim_beh.exe.sim/work/a_2734820196_0181651160.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/pr.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439989832805790689_503743352(char *, char *, char *, char *, char *, char *);
char *ieee_p_2592010699_sub_207919886985903570_503743352(char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_2734820196_0181651160_p_0(char *t0)
{
char t1[16];
char t4[16];
char *t2;
char *t3;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 7008U);
t5 = (t0 + 1192U);
t6 = *((char **)t5);
t5 = (t0 + 7008U);
t7 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t4, t6, t5);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t3, t2, t7, t4);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4840);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4696);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_2734820196_0181651160_p_1(char *t0)
{
char t1[16];
char t2[16];
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(19, ng0);
LAB3: t3 = (t0 + 1032U);
t4 = *((char **)t3);
t3 = (t0 + 7008U);
t5 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t2, t4, t3);
t6 = (t0 + 1192U);
t7 = *((char **)t6);
t6 = (t0 + 7008U);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t5, t2, t7, t6);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4904);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4712);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_2734820196_0181651160_p_2(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(21, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t1 = (t0 + 4968);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 4728);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_2734820196_0181651160_p_3(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(22, ng0);
LAB3: t1 = (t0 + 1992U);
t2 = *((char **)t1);
t1 = (t0 + 5032);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 4744);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_2734820196_0181651160_p_4(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
int t19;
int t20;
unsigned int t21;
unsigned int t22;
unsigned int t23;
char *t24;
unsigned char t25;
unsigned char t26;
unsigned char t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(27, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(28, ng0);
t1 = (t0 + 7117);
*((int *)t1) = 7;
t2 = (t0 + 7121);
*((int *)t2) = 0;
t3 = 7;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(31, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5096);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast_port(t1);
t1 = (t0 + 4760);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(29, ng0);
t5 = (t0 + 2408U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1832U);
t8 = *((char **)t5);
t5 = (t0 + 7117);
t9 = *((int *)t5);
t10 = (t9 - 7);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t15);
t17 = (t0 + 1992U);
t18 = *((char **)t17);
t17 = (t0 + 7117);
t19 = *((int *)t17);
t20 = (t19 - 7);
t21 = (t20 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t17));
t22 = (1U * t21);
t23 = (0 + t22);
t24 = (t18 + t23);
t25 = *((unsigned char *)t24);
t26 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t16, t25);
t27 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t26);
t28 = (t0 + 2408U);
t29 = *((char **)t28);
t28 = (t29 + 0);
*((unsigned char *)t28) = t27;
LAB4: t1 = (t0 + 7117);
t3 = *((int *)t1);
t2 = (t0 + 7121);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7117);
*((int *)t5) = t3;
goto LAB2;
}
extern void work_a_2734820196_0181651160_init()
{
static char *pe[] = {(void *)work_a_2734820196_0181651160_p_0,(void *)work_a_2734820196_0181651160_p_1,(void *)work_a_2734820196_0181651160_p_2,(void *)work_a_2734820196_0181651160_p_3,(void *)work_a_2734820196_0181651160_p_4};
xsi_register_didat("work_a_2734820196_0181651160", "isim/pr_isim_beh.exe.sim/work/a_2734820196_0181651160.didat");
xsi_register_executes(pe);
}

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isim/pr_isim_beh.exe.sim/work/a_2734820196_0181651160.lin64.o Normal file
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39
isim/pr_isim_beh.exe.sim/work/pr_isim_beh.exe_main.c Normal file
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@@ -0,0 +1,39 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_2734820196_0181651160_init();
xsi_register_tops("work_a_2734820196_0181651160");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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isim/pr_isim_beh.exe.sim/work/pr_isim_beh.exe_main.lin64.o Normal file
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24
isim/precompiled.exe.sim/ieee/p_2592010699.c
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@@ -723,7 +723,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7736);
LAB9: t46 = (t1 + 7752);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -999,7 +999,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7801);
LAB9: t46 = (t1 + 7817);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -1280,7 +1280,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7866);
LAB9: t46 = (t1 + 7882);
xsi_report(t46, 66U, (unsigned char)3);
goto LAB10;
@@ -1571,7 +1571,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7932);
LAB9: t46 = (t1 + 7948);
xsi_report(t46, 66U, (unsigned char)3);
goto LAB10;
@@ -1853,7 +1853,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7998);
LAB9: t46 = (t1 + 8014);
xsi_report(t46, 64U, (unsigned char)3);
goto LAB10;
@@ -2129,7 +2129,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8062);
LAB9: t46 = (t1 + 8078);
xsi_report(t46, 64U, (unsigned char)3);
goto LAB10;
@@ -2410,7 +2410,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8126);
LAB9: t46 = (t1 + 8142);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -2701,7 +2701,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8191);
LAB9: t46 = (t1 + 8207);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -2983,7 +2983,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8256);
LAB9: t46 = (t1 + 8272);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -3259,7 +3259,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8321);
LAB9: t46 = (t1 + 8337);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -3540,7 +3540,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8386);
LAB9: t46 = (t1 + 8402);
xsi_report(t46, 66U, (unsigned char)3);
goto LAB10;
@@ -3831,7 +3831,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8452);
LAB9: t46 = (t1 + 8468);
xsi_report(t46, 66U, (unsigned char)3);
goto LAB10;

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isim/precompiled.exe.sim/ieee/p_2592010699.didat
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isim/precompiled.exe.sim/ieee/p_2592010699.lin64.o
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0
isim/tb_isim_beh.exe.sim/isimcrash.log Normal file
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28
isim/tb_isim_beh.exe.sim/isimkernel.log Normal file
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@@ -0,0 +1,28 @@
Command line:
tb_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 49451
Tue Aug 27 09:36:05 2019
Elaboration Time: 0.12 sec
Current Memory Usage: 198.607 Meg
Total Signals : 13
Total Nets : 50
Total Signal Drivers : 6
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 7
Total Traceable Variables : 10
Total Scalar Nets and Variables : 412
Total Simulation Time: 0.13 sec
Current Memory Usage: 276.206 Meg
Tue Aug 27 09:36:11 2019

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374
isim/tb_isim_beh.exe.sim/work/a_3230118638_0181651160.c Normal file
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@@ -0,0 +1,374 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/pr.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439989832805790689_503743352(char *, char *, char *, char *, char *, char *);
char *ieee_p_2592010699_sub_207919886985903570_503743352(char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_3230118638_0181651160_p_0(char *t0)
{
char t1[16];
char t4[16];
char *t2;
char *t3;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 7176U);
t5 = (t0 + 1192U);
t6 = *((char **)t5);
t5 = (t0 + 7192U);
t7 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t4, t6, t5);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t3, t2, t7, t4);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4960);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4816);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_3230118638_0181651160_p_1(char *t0)
{
char t1[16];
char t2[16];
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(19, ng0);
LAB3: t3 = (t0 + 1032U);
t4 = *((char **)t3);
t3 = (t0 + 7176U);
t5 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t2, t4, t3);
t6 = (t0 + 1192U);
t7 = *((char **)t6);
t6 = (t0 + 7192U);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t5, t2, t7, t6);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 5024);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4832);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_3230118638_0181651160_p_2(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(21, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t1 = (t0 + 5088);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 4848);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_3230118638_0181651160_p_3(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(22, ng0);
LAB3: t1 = (t0 + 1992U);
t2 = *((char **)t1);
t1 = (t0 + 5152);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 4864);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_3230118638_0181651160_p_4(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
int t5;
char *t6;
char *t7;
unsigned char t8;
char *t9;
int t10;
int t11;
unsigned int t12;
unsigned int t13;
unsigned int t14;
char *t15;
unsigned char t16;
unsigned char t17;
char *t18;
char *t19;
int t20;
int t21;
unsigned int t22;
unsigned int t23;
unsigned int t24;
char *t25;
unsigned char t26;
unsigned char t27;
char *t28;
char *t29;
unsigned char t30;
unsigned char t31;
unsigned char t32;
char *t33;
LAB0: xsi_set_current_line(28, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(29, ng0);
t1 = (t0 + 2528U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(30, ng0);
t3 = (8 - 1);
t1 = (t0 + 7318);
*((int *)t1) = t3;
t2 = (t0 + 7322);
*((int *)t2) = 0;
t4 = t3;
t5 = 0;
LAB2: if (t4 >= t5)
goto LAB3;
LAB5: xsi_set_current_line(34, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 5216);
t6 = (t1 + 56U);
t7 = *((char **)t6);
t9 = (t7 + 56U);
t15 = *((char **)t9);
*((unsigned char *)t15) = t8;
xsi_driver_first_trans_fast_port(t1);
t1 = (t0 + 4880);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(31, ng0);
t6 = (t0 + 2408U);
t7 = *((char **)t6);
t8 = *((unsigned char *)t7);
t6 = (t0 + 1832U);
t9 = *((char **)t6);
t6 = (t0 + 7318);
t10 = *((int *)t6);
t11 = (t10 - 7);
t12 = (t11 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t6));
t13 = (1U * t12);
t14 = (0 + t13);
t15 = (t9 + t14);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16);
t18 = (t0 + 1992U);
t19 = *((char **)t18);
t18 = (t0 + 7318);
t20 = *((int *)t18);
t21 = (t20 - 7);
t22 = (t21 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t18));
t23 = (1U * t22);
t24 = (0 + t23);
t25 = (t19 + t24);
t26 = *((unsigned char *)t25);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t17, t26);
t28 = (t0 + 2528U);
t29 = *((char **)t28);
t30 = *((unsigned char *)t29);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t27, t30);
t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t8, t31);
t28 = (t0 + 2408U);
t33 = *((char **)t28);
t28 = (t33 + 0);
*((unsigned char *)t28) = t32;
xsi_set_current_line(32, ng0);
t1 = (t0 + 2528U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 1832U);
t6 = *((char **)t1);
t1 = (t0 + 7318);
t3 = *((int *)t1);
t10 = (t3 - 7);
t12 = (t10 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t1));
t13 = (1U * t12);
t14 = (0 + t13);
t7 = (t6 + t14);
t16 = *((unsigned char *)t7);
t9 = (t0 + 1992U);
t15 = *((char **)t9);
t9 = (t0 + 7318);
t11 = *((int *)t9);
t20 = (t11 - 7);
t22 = (t20 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t9));
t23 = (1U * t22);
t24 = (0 + t23);
t18 = (t15 + t24);
t17 = *((unsigned char *)t18);
t26 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t17);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t16, t26);
t30 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t27);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t30);
t19 = (t0 + 2528U);
t25 = *((char **)t19);
t19 = (t25 + 0);
*((unsigned char *)t19) = t31;
LAB4: t1 = (t0 + 7318);
t4 = *((int *)t1);
t2 = (t0 + 7322);
t5 = *((int *)t2);
if (t4 == t5)
goto LAB5;
LAB6: t3 = (t4 + -1);
t4 = t3;
t6 = (t0 + 7318);
*((int *)t6) = t4;
goto LAB2;
}
extern void work_a_3230118638_0181651160_init()
{
static char *pe[] = {(void *)work_a_3230118638_0181651160_p_0,(void *)work_a_3230118638_0181651160_p_1,(void *)work_a_3230118638_0181651160_p_2,(void *)work_a_3230118638_0181651160_p_3,(void *)work_a_3230118638_0181651160_p_4};
xsi_register_didat("work_a_3230118638_0181651160", "isim/tb_isim_beh.exe.sim/work/a_3230118638_0181651160.didat");
xsi_register_executes(pe);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/tb.vhd";
static void work_a_3671711236_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 3104U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(81, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(82, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(83, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(84, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_3671711236_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
LAB0: t1 = (t0 + 3352U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(92, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 3160);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(94, ng0);
t2 = (t0 + 2128U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 3160);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(98, ng0);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: goto LAB2;
LAB13: goto LAB12;
LAB15: goto LAB13;
}
extern void work_a_3671711236_2372691052_init()
{
static char *pe[] = {(void *)work_a_3671711236_2372691052_p_0,(void *)work_a_3671711236_2372691052_p_1};
xsi_register_didat("work_a_3671711236_2372691052", "isim/tb_isim_beh.exe.sim/work/a_3671711236_2372691052.didat");
xsi_register_executes(pe);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_3230118638_0181651160_init();
work_a_3671711236_2372691052_init();
xsi_register_tops("work_a_3671711236_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pr is
generic( BITCOUNT: integer := 8 );
port(
xExp, yExp: in std_logic_vector((BITCOUNT-1) downto 0);
xOut, yOut: out std_logic_vector((BITCOUNT-1) downto 0);
needSwap: out std_logic
);
end pr;
architecture qwe of pr is
signal xGTy: std_logic_vector((BITCOUNT-1) downto 0);
signal yGTx: std_logic_vector((BITCOUNT-1) downto 0);
begin
xGTy <= xExp and (not yExp);
yGTx <= (not xExp) and yExp;
xOut <= xGTy;
yOut <= yGTx;
needSwap_compute: process (xGTy, yGTx)
variable SW: std_logic;
variable K: std_logic;
begin
SW := '0';
k := '1';
for i in (BITCOUNT-1) downto 0 loop
SW := SW or ((not(xGTy(i)) and yGTx(i)) and K);
K := K and (not(xGTy(i) and not(yGTx(i))));
end loop;
needSwap <= SW;
end process;
end qwe;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:37:57 08/27/2019
-- Design Name:
-- Module Name: /home/ise/gianni/IEEE754Adder/tb.vhd
-- Project Name: IEEE754Adder
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: pr
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE behavior OF tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pr
PORT(
xExp : IN std_logic_vector(7 downto 0);
yExp : IN std_logic_vector(7 downto 0);
xOut : OUT std_logic_vector(7 downto 0);
yOut : OUT std_logic_vector(7 downto 0);
needSwap : OUT std_logic
);
END COMPONENT;
--Inputs
signal xExp : std_logic_vector(7 downto 0) := "01010101";
signal yExp : std_logic_vector(7 downto 0) := "01010001";
--Outputs
signal xOut : std_logic_vector(7 downto 0);
signal yOut : std_logic_vector(7 downto 0);
signal needSwap : std_logic;
signal clock: std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pr PORT MAP (
xExp => xExp,
yExp => yExp,
xOut => xOut,
yOut => yOut,
needSwap => needSwap
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
END;

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xilinxsim.ini
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work=isim/work
isim_temp=isim/temp