29 lines
571 B
VHDL
29 lines
571 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity EqualCheck is
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generic( BITCOUNT: integer := 8 );
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port(
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X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
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isEqual: out std_logic
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);
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end EqualCheck;
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architecture EqualCheckArch of EqualCheck is
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signal compVec: std_logic_vector( (BITCOUNT-1) downto 0 );
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begin
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compVec <= X xor Y;
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res_compute: process (compVec)
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variable res_tmp: std_logic;
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begin
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res_tmp := '0';
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for i in compVec'range loop
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res_tmp := res_tmp or compVec(i);
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end loop;
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isEqual <= not res_tmp;
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end process;
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end EqualCheckArch;
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