21 lines
325 B
VHDL
21 lines
325 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity AddSub is
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generic( BITCOUNT: integer := 8 );
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port(
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X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
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isSub: in std_logic := 0;
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result: out std_logic_vector((BITCOUNT-1) downto 0)
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);
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end AddSub;
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architecture CLAAddSubArch of AddSub is
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begin
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end CLAAddSubArch;
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