19 lines
295 B
VHDL
19 lines
295 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity FullAdder is
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port(
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X, Y, C_IN : in std_logic;
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S, C_OUT : out std_logic
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);
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end FullAdder;
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architecture FullAdderArch of FullAdder is
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begin
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S <= C_IN xor X xor Y;
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C_OUT <= (C_IN and X) or (C_IN and Y) or (X and Y);
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end FullAdderArch;
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