60 lines
1.3 KiB
VHDL
60 lines
1.3 KiB
VHDL
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY AdderTest IS
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END AdderTest;
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ARCHITECTURE behavior OF AdderTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Adder
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PORT(
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X : IN std_logic_vector(7 downto 0);
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Y : IN std_logic_vector(7 downto 0);
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carry_in : IN std_logic;
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result : OUT std_logic_vector(7 downto 0);
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carry_out : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal X : std_logic_vector(7 downto 0) := (others => '0');
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signal Y : std_logic_vector(7 downto 0) := (others => '0');
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signal carry_in : std_logic := '0';
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--Outputs
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signal result : std_logic_vector(7 downto 0);
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signal carry_out : std_logic;
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-- No clocks detected in port list. Replace clock below with
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-- appropriate port name
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signal clock: std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Adder PORT MAP (
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X => X,
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Y => Y,
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carry_in => carry_in,
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result => result,
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carry_out => carry_out
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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x <= "00010101";
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y <= "00001110";
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END;
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