IEEE754Adder/AddSubTest_isim_beh.wdb

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/home/Luca/ISE/IEEE754Adder/AddSubTest.vhd/opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ieee/std_logic_1164.vhd/home/Luca/ISE/IEEE754Adder/AddSub.vhd/home/Luca/ISE/IEEE754Adder/Adder.vhdstd_ulogic'U''X''0''1''Z''W''L''H''-'std_ulogic_vectorstd_logic'U''X''0''1''Z''W''L''H''-'std_logic_vectorx01'X''0''1'x01z'X''0''1''Z'ux01'U''X''0''1'ux01z'U''X''0''1''Z'stdlogic_1dBasestdlogic_1dstdlogic_tableBasestdlogic_tablelogic_x01_tableBaselogic_x01_tablelogic_x01z_tableBaselogic_x01z_tablelogic_ux01_tableBaselogic_ux01_table_top_topaddsubtestaddsubtestbehaviorxyissubresultoverflowclockclock_periodtimefspsnsusmssecminhrstd_logic_1164std_logic_1164resolution_table/build/xfndry10/P.20131013/rtf/vhdl/src/ieee/std_logic_1164.vhdand_tableor_tablexor_tablenot_tablecvt_to_x01cvt_to_x01zcvt_to_ux01uutAddSubAddSubArchxyissubresultoverflowy2c_outbitcountinteger:clock_processaddsubtest:test_procaddsubtestADDAdderCarryLookAheadArchxycarry_inresultcarry_outgenerationpropagationcarrysum_no_carrybitcount:y2procAddSub:41AddSub:21Adder:22Adder:23Adder:carry_look_aheadAdderc:36Adder:37Adder