297 lines
10 KiB
Plaintext
297 lines
10 KiB
Plaintext
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Release 14.7 - xst P.20131013 (lin64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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-->
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Reading design: TypeCheck.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "TypeCheck.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "TypeCheck"
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Output Format : NGC
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Target Device : xc3s50-5-pq208
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---- Source Options
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Top Module Name : TypeCheck
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work.
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Architecture typecheckarch of Entity typecheck is up to date.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity <TypeCheck> in library <work> (architecture <typecheckarch>).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <TypeCheck> in library <work> (Architecture <typecheckarch>).
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Entity <TypeCheck> analyzed. Unit <TypeCheck> generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <TypeCheck>.
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Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd".
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WARNING:Xst:647 - Input <N<31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Unit <TypeCheck> synthesized.
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=========================================================================
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HDL Synthesis Report
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Found no macro
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Found no macro
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <TypeCheck> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block TypeCheck, actual ratio is 0.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Found no macro
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : TypeCheck.ngr
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Top Level Output File Name : TypeCheck
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : No
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Design Statistics
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# IOs : 34
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Cell Usage :
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# BELS : 18
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# GND : 1
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# LUT3 : 3
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# LUT4 : 7
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# MUXCY : 6
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# VCC : 1
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# IO Buffers : 33
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# IBUF : 31
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# OBUF : 2
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 3s50pq208-5
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Number of Slices: 5 out of 768 0%
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Number of 4 input LUTs: 10 out of 1536 0%
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Number of IOs: 34
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Number of bonded IOBs: 33 out of 124 26%
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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No clock signals found in this design
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -5
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Minimum period: No path found
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Minimum input arrival time before clock: No path found
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Maximum output required time after clock: No path found
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Maximum combinational path delay: 9.965ns
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default path analysis
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Total number of paths / destination ports: 62 / 2
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-------------------------------------------------------------------------
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Delay: 9.965ns (Levels of Logic = 10)
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Source: N<3> (PAD)
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Destination: NaN (PAD)
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Data Path: N<3> to NaN
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 1 0.715 0.976 N_3_IBUF (N_3_IBUF)
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LUT3:I0->O 1 0.479 0.000 T_wg_lut<0> (T_wg_lut<0>)
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MUXCY:S->O 1 0.435 0.000 T_wg_cy<0> (T_wg_cy<0>)
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MUXCY:CI->O 1 0.056 0.000 T_wg_cy<1> (T_wg_cy<1>)
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MUXCY:CI->O 1 0.056 0.000 T_wg_cy<2> (T_wg_cy<2>)
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MUXCY:CI->O 1 0.056 0.000 T_wg_cy<3> (T_wg_cy<3>)
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MUXCY:CI->O 1 0.056 0.000 T_wg_cy<4> (T_wg_cy<4>)
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MUXCY:CI->O 2 0.265 0.804 T_wg_cy<5> (T)
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LUT3:I2->O 1 0.479 0.681 NaN1 (NaN_OBUF)
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OBUF:I->O 4.909 NaN_OBUF (NaN)
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----------------------------------------
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Total 9.965ns (7.503ns logic, 2.461ns route)
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(75.3% logic, 24.7% route)
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=========================================================================
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Total REAL time to Xst completion: 3.00 secs
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Total CPU time to Xst completion: 3.06 secs
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-->
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Total memory usage is 605836 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 1 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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