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/home/ise/gianni/IEEE754Adder/FullAdderTest.vhd/opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ieee/std_logic_1164.vhd/home/ise/gianni/IEEE754Adder/FullAdder.vhdstd_ulogic'U''X''0''1''Z''W''L''H''-'std_ulogic_vectorstd_logic'U''X''0''1''Z''W''L''H''-'std_logic_vectorx01'X''0''1'x01z'X''0''1''Z'ux01'U''X''0''1'ux01z'U''X''0''1''Z'stdlogic_1dBasestdlogic_1dstdlogic_tableBasestdlogic_tablelogic_x01_tableBaselogic_x01_tablelogic_x01z_tableBaselogic_x01z_tablelogic_ux01_tableBaselogic_ux01_table_top_topfulladdertestfulladdertestbehaviorxyc_insc_outclockclock_periodtimefspsnsusmssecminhrstd_logic_1164std_logic_1164resolution_table/build/legacysi10/P.20160913/rtf/vhdl/src/ieee/std_logic_1164.vhdand_tableor_tablexor_tablenot_tablecvt_to_x01cvt_to_x01zcvt_to_ux01uutFullAdderFullAdderArchxyc_insc_out:clock_processfulladdertest:test_processfulladdertest:14FullAdder:15FullAdder