35 lines
750 B
VHDL
35 lines
750 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Comparator is
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generic( BITCOUNT: integer := 8 );
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port(
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xT, yT: in std_logic_vector((BITCOUNT-1) downto 0);
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needSwap: out std_logic
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);
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end Comparator;
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architecture ComparatorArch of Comparator is
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signal xGTy: std_logic_vector((BITCOUNT-1) downto 0);
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signal yGTx: std_logic_vector((BITCOUNT-1) downto 0);
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begin
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xGTy <= xT and (not yT);
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yGTx <= (not xT) and yT;
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needSwap_compute: process (xGTy, yGTx)
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variable SW: std_logic;
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variable K: std_logic;
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begin
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SW := '0';
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K := '1';
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for i in (BITCOUNT-1) downto 0 loop
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SW := SW or ((not(xGTy(i)) and yGTx(i)) and K);
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K := K and (not(xGTy(i) and not(yGTx(i))));
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end loop;
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needSwap <= SW;
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end process;
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end ComparatorArch;
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