32 lines
662 B
VHDL
32 lines
662 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity TwoComplement is
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generic(BITCOUNT : integer := 8);
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port(
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DIFF_EXP_C2 : in std_logic_vector((BITCOUNT-1) downto 0);
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DIFF_EXP_ABS : out std_logic_vector((BITCOUNT-2) downto 0);
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);
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end TwoComplement;
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architecture TwoComplementArch of TwoComplement is
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signal S : std_logic;
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signal M : std_logic_vector((BITCOUNT-2) downto 0);
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begin
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S <= DIFF_EXP_C2(BITCOUNT-1);
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M <= DIFF_EXP_C2((BITCOUNT-2) downto 0);
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C2 : process(DIFF_EXP_C2)
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begin
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for i in (BITCOUNT-2) downto 0 loop
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M(i) <= S xor M(i);
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end loop;
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end process;
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--sommare 1 a M se S = '1'
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DIFF_EXP_ABS <= M;
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end TwoComplementArch;
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