31 lines
1.8 KiB
Plaintext
31 lines
1.8 KiB
Plaintext
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_beh.prj work.SpecialCasesTest
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ISim P.20131013 (signature 0xfbc00daa)
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Number of CPUs detected in this system: 4
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Turning on mult-threading, number of parallel sub-compilation jobs: 8
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Determining compilation order of HDL files
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest.vhd" into library work
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Starting static elaboration
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Completed static elaboration
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Fuse Memory Usage: 94420 KB
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Fuse CPU Usage: 980 ms
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Compiling package standard
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Compiling package std_logic_1164
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Compiling architecture typecheckarch of entity TypeCheck [typecheck_default]
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Compiling architecture nancheckarch of entity NaNCheck [nancheck_default]
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Compiling architecture equalcheckarch of entity EqualCheck [\EqualCheck(31)\]
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Compiling architecture zerocheckarch of entity ZeroCheck [zerocheck_default]
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Compiling architecture specialcasescheckarch of entity SpecialCasesCheck [specialcasescheck_default]
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Compiling architecture behavior of entity specialcasestest
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Time Resolution for simulation is 1ps.
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 13 VHDL Units
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Built simulation executable /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe
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Fuse Memory Usage: 658120 KB
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Fuse CPU Usage: 1000 ms
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GCC CPU Usage: 280 ms
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