299 lines
10 KiB
Plaintext
299 lines
10 KiB
Plaintext
|
Release 14.7 - xst P.20131013 (lin64)
|
||
|
|
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||
|
|
-->
|
||
|
|
Parameter TMPDIR set to xst/projnav.tmp
|
||
|
|
|
||
|
|
|
||
|
|
Total REAL time to Xst completion: 0.00 secs
|
||
|
|
Total CPU time to Xst completion: 0.05 secs
|
||
|
|
|
||
|
|
-->
|
||
|
|
Parameter xsthdpdir set to xst
|
||
|
|
|
||
|
|
|
||
|
|
Total REAL time to Xst completion: 0.00 secs
|
||
|
|
Total CPU time to Xst completion: 0.05 secs
|
||
|
|
|
||
|
|
-->
|
||
|
|
Reading design: equalCheck.prj
|
||
|
|
|
||
|
|
TABLE OF CONTENTS
|
||
|
|
1) Synthesis Options Summary
|
||
|
|
2) HDL Parsing
|
||
|
|
3) HDL Elaboration
|
||
|
|
4) HDL Synthesis
|
||
|
|
4.1) HDL Synthesis Report
|
||
|
|
5) Advanced HDL Synthesis
|
||
|
|
5.1) Advanced HDL Synthesis Report
|
||
|
|
6) Low Level Synthesis
|
||
|
|
7) Partition Report
|
||
|
|
8) Design Summary
|
||
|
|
8.1) Primitive and Black Box Usage
|
||
|
|
8.2) Device utilization summary
|
||
|
|
8.3) Partition Resource Summary
|
||
|
|
8.4) Timing Report
|
||
|
|
8.4.1) Clock Information
|
||
|
|
8.4.2) Asynchronous Control Signals Information
|
||
|
|
8.4.3) Timing Summary
|
||
|
|
8.4.4) Timing Details
|
||
|
|
8.4.5) Cross Clock Domains Report
|
||
|
|
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* Synthesis Options Summary *
|
||
|
|
=========================================================================
|
||
|
|
---- Source Parameters
|
||
|
|
Input File Name : "equalCheck.prj"
|
||
|
|
Ignore Synthesis Constraint File : NO
|
||
|
|
|
||
|
|
---- Target Parameters
|
||
|
|
Output File Name : "equalCheck"
|
||
|
|
Output Format : NGC
|
||
|
|
Target Device : xa6slx4-3-csg225
|
||
|
|
|
||
|
|
---- Source Options
|
||
|
|
Top Module Name : equalCheck
|
||
|
|
Automatic FSM Extraction : YES
|
||
|
|
FSM Encoding Algorithm : Auto
|
||
|
|
Safe Implementation : No
|
||
|
|
FSM Style : LUT
|
||
|
|
RAM Extraction : Yes
|
||
|
|
RAM Style : Auto
|
||
|
|
ROM Extraction : Yes
|
||
|
|
Shift Register Extraction : YES
|
||
|
|
ROM Style : Auto
|
||
|
|
Resource Sharing : YES
|
||
|
|
Asynchronous To Synchronous : NO
|
||
|
|
Shift Register Minimum Size : 2
|
||
|
|
Use DSP Block : Auto
|
||
|
|
Automatic Register Balancing : No
|
||
|
|
|
||
|
|
---- Target Options
|
||
|
|
LUT Combining : Auto
|
||
|
|
Reduce Control Sets : Auto
|
||
|
|
Add IO Buffers : YES
|
||
|
|
Global Maximum Fanout : 100000
|
||
|
|
Add Generic Clock Buffer(BUFG) : 32
|
||
|
|
Register Duplication : YES
|
||
|
|
Optimize Instantiated Primitives : NO
|
||
|
|
Use Clock Enable : Yes
|
||
|
|
Use Synchronous Set : Yes
|
||
|
|
Use Synchronous Reset : Yes
|
||
|
|
Pack IO Registers into IOBs : Auto
|
||
|
|
Equivalent register Removal : YES
|
||
|
|
|
||
|
|
---- General Options
|
||
|
|
Optimization Goal : Speed
|
||
|
|
Optimization Effort : 1
|
||
|
|
Power Reduction : NO
|
||
|
|
Keep Hierarchy : No
|
||
|
|
Netlist Hierarchy : As_Optimized
|
||
|
|
RTL Output : Yes
|
||
|
|
Global Optimization : AllClockNets
|
||
|
|
Read Cores : YES
|
||
|
|
Write Timing Constraints : NO
|
||
|
|
Cross Clock Analysis : NO
|
||
|
|
Hierarchy Separator : /
|
||
|
|
Bus Delimiter : <>
|
||
|
|
Case Specifier : Maintain
|
||
|
|
Slice Utilization Ratio : 100
|
||
|
|
BRAM Utilization Ratio : 100
|
||
|
|
DSP48 Utilization Ratio : 100
|
||
|
|
Auto BRAM Packing : NO
|
||
|
|
Slice Utilization Ratio Delta : 5
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* HDL Parsing *
|
||
|
|
=========================================================================
|
||
|
|
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/equalCheck.vhd" into library work
|
||
|
|
Parsing entity <equalCheck>.
|
||
|
|
Parsing architecture <equalCheckArch> of entity <equalcheck>.
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* HDL Elaboration *
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
Elaborating entity <equalCheck> (architecture <equalCheckArch>) with generics from library <work>.
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* HDL Synthesis *
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
Synthesizing Unit <equalCheck>.
|
||
|
|
Related source file is "/home/Luca/ISE/IEEE754Adder/equalCheck.vhd".
|
||
|
|
BITCOUNT = 8
|
||
|
|
Summary:
|
||
|
|
Unit <equalCheck> synthesized.
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
HDL Synthesis Report
|
||
|
|
|
||
|
|
Macro Statistics
|
||
|
|
# Xors : 1
|
||
|
|
8-bit xor2 : 1
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* Advanced HDL Synthesis *
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
Advanced HDL Synthesis Report
|
||
|
|
|
||
|
|
Macro Statistics
|
||
|
|
# Xors : 1
|
||
|
|
8-bit xor2 : 1
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* Low Level Synthesis *
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
Optimizing unit <equalCheck> ...
|
||
|
|
|
||
|
|
Mapping all equations...
|
||
|
|
Building and optimizing final netlist ...
|
||
|
|
Found area constraint ratio of 100 (+ 5) on block equalCheck, actual ratio is 0.
|
||
|
|
|
||
|
|
Final Macro Processing ...
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
Final Register Report
|
||
|
|
|
||
|
|
Found no macro
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* Partition Report *
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
Partition Implementation Status
|
||
|
|
-------------------------------
|
||
|
|
|
||
|
|
No Partitions were found in this design.
|
||
|
|
|
||
|
|
-------------------------------
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* Design Summary *
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
Top Level Output File Name : equalCheck.ngc
|
||
|
|
|
||
|
|
Primitive and Black Box Usage:
|
||
|
|
------------------------------
|
||
|
|
# BELS : 4
|
||
|
|
# LUT5 : 1
|
||
|
|
# LUT6 : 3
|
||
|
|
# IO Buffers : 17
|
||
|
|
# IBUF : 16
|
||
|
|
# OBUF : 1
|
||
|
|
|
||
|
|
Device utilization summary:
|
||
|
|
---------------------------
|
||
|
|
|
||
|
|
Selected Device : xa6slx4csg225-3
|
||
|
|
|
||
|
|
|
||
|
|
Slice Logic Utilization:
|
||
|
|
Number of Slice LUTs: 4 out of 2400 0%
|
||
|
|
Number used as Logic: 4 out of 2400 0%
|
||
|
|
|
||
|
|
Slice Logic Distribution:
|
||
|
|
Number of LUT Flip Flop pairs used: 4
|
||
|
|
Number with an unused Flip Flop: 4 out of 4 100%
|
||
|
|
Number with an unused LUT: 0 out of 4 0%
|
||
|
|
Number of fully used LUT-FF pairs: 0 out of 4 0%
|
||
|
|
Number of unique control sets: 0
|
||
|
|
|
||
|
|
IO Utilization:
|
||
|
|
Number of IOs: 17
|
||
|
|
Number of bonded IOBs: 17 out of 132 12%
|
||
|
|
|
||
|
|
Specific Feature Utilization:
|
||
|
|
|
||
|
|
---------------------------
|
||
|
|
Partition Resource Summary:
|
||
|
|
---------------------------
|
||
|
|
|
||
|
|
No Partitions were found in this design.
|
||
|
|
|
||
|
|
---------------------------
|
||
|
|
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
Timing Report
|
||
|
|
|
||
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
||
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
||
|
|
|
||
|
|
Clock Information:
|
||
|
|
------------------
|
||
|
|
No clock signals found in this design
|
||
|
|
|
||
|
|
Asynchronous Control Signals Information:
|
||
|
|
----------------------------------------
|
||
|
|
No asynchronous control signals found in this design
|
||
|
|
|
||
|
|
Timing Summary:
|
||
|
|
---------------
|
||
|
|
Speed Grade: -3
|
||
|
|
|
||
|
|
Minimum period: No path found
|
||
|
|
Minimum input arrival time before clock: No path found
|
||
|
|
Maximum output required time after clock: No path found
|
||
|
|
Maximum combinational path delay: 7.658ns
|
||
|
|
|
||
|
|
Timing Details:
|
||
|
|
---------------
|
||
|
|
All values displayed in nanoseconds (ns)
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
Timing constraint: Default path analysis
|
||
|
|
Total number of paths / destination ports: 20 / 1
|
||
|
|
-------------------------------------------------------------------------
|
||
|
|
Delay: 7.658ns (Levels of Logic = 5)
|
||
|
|
Source: X<7> (PAD)
|
||
|
|
Destination: isEqual (PAD)
|
||
|
|
|
||
|
|
Data Path: X<7> to isEqual
|
||
|
|
Gate Net
|
||
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||
|
|
---------------------------------------- ------------
|
||
|
|
IBUF:I->O 1 1.222 0.944 X_7_IBUF (X_7_IBUF)
|
||
|
|
LUT6:I0->O 1 0.203 0.924 isEqual<0>4 (isEqual<0>3)
|
||
|
|
LUT5:I0->O 1 0.203 0.808 isEqual<0>5_SW0 (N2)
|
||
|
|
LUT6:I3->O 1 0.205 0.579 isEqual<0>5 (isEqual_OBUF)
|
||
|
|
OBUF:I->O 2.571 isEqual_OBUF (isEqual)
|
||
|
|
----------------------------------------
|
||
|
|
Total 7.658ns (4.404ns logic, 3.254ns route)
|
||
|
|
(57.5% logic, 42.5% route)
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
Cross Clock Domains Report:
|
||
|
|
--------------------------
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
|
||
|
|
Total REAL time to Xst completion: 3.00 secs
|
||
|
|
Total CPU time to Xst completion: 3.71 secs
|
||
|
|
|
||
|
|
-->
|
||
|
|
|
||
|
|
|
||
|
|
Total memory usage is 474280 kilobytes
|
||
|
|
|
||
|
|
Number of errors : 0 ( 0 filtered)
|
||
|
|
Number of warnings : 0 ( 0 filtered)
|
||
|
|
Number of infos : 0 ( 0 filtered)
|
||
|
|
|