61 lines
1.5 KiB
VHDL
61 lines
1.5 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity ZeroCounter is
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generic(
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BITCOUNT : integer := 8;
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RES_BITCOUNT : integer := 3 -- MUST BE >= CEIL( LOG2( BITCOUNT ) )
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);
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port(
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X : in std_logic_vector( (BITCOUNT-1) downto 0 );
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Z_COUNT : out std_logic_vector( (RES_BITCOUNT-1) downto 0 );
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ALL_ZEROS : out std_logic
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);
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end ZeroCounter;
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architecture ZeroCounterArch of ZeroCounter is
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begin
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ZEROCOUNT_PROCESS: process (X)
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variable ZC: std_logic_vector((RES_BITCOUNT-1) downto 0);
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variable BIN_N: std_logic_vector((RES_BITCOUNT-1) downto 0);
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variable PART_ZC: std_logic_vector((BITCOUNT-1) downto 0);
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begin
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ZC := ((RES_BITCOUNT-1) downto 0 => '0');
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PART_ZC := ((BITCOUNT-1) downto 0 => '1');
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for N in 1 to (BITCOUNT-1) loop
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-- compute partial logic to add to result's '1' bits
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for p_i in (BITCOUNT-1) downto (BITCOUNT-N) loop
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PART_ZC(N) := PART_ZC(N) and (not X(p_i));
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end loop;
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PART_ZC(N) := PART_ZC(N) and X(BITCOUNT-1-N);
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-- add partial logic to result
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BIN_N := std_logic_vector(to_unsigned(N, BIN_N'length));
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for res_i in (RES_BITCOUNT-1) downto 0 loop
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if ( BIN_N(res_i) = '1' ) then
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ZC(res_i) := ZC(res_i) or PART_ZC(N);
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end if;
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end loop;
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end loop;
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Z_COUNT <= ZC;
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end process;
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ALLZERO_PROCESS: process (X)
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variable AZ : std_logic;
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begin
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AZ := '1';
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for i in X'range loop
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AZ := AZ and (not X(i));
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end loop;
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ALL_ZEROS <= AZ;
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end process;
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end ZeroCounterArch;
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