69 lines
1.3 KiB
VHDL
69 lines
1.3 KiB
VHDL
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY OperationCheckTest IS
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END OperationCheckTest;
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ARCHITECTURE behavior OF OperationCheckTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT OperationCheck
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PORT(
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X_SIGN : IN std_logic;
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Y_SIGN : IN std_logic;
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OP : OUT std_logic;
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RES_SIGN : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal X_SIGN : std_logic := '0';
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signal Y_SIGN : std_logic := '0';
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--Outputs
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signal OP : std_logic;
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signal RES_SIGN : std_logic;
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signal clock : std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: OperationCheck PORT MAP (
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X_SIGN => X_SIGN,
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Y_SIGN => Y_SIGN,
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OP => OP,
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RES_SIGN => RES_SIGN
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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test_proc: process
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begin
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X_SIGN <= '0';
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Y_SIGN <= '0';
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wait for clock_period;
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X_SIGN <= '0';
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Y_SIGN <= '1';
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wait for clock_period;
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X_SIGN <= '1';
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Y_SIGN <= '0';
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wait for clock_period;
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X_SIGN <= '1';
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Y_SIGN <= '1';
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wait for clock_period;
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end process;
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END;
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