36 lines
563 B
VHDL
36 lines
563 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity FlipFlopDVector is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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CLK : in std_logic;
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RESET : in std_logic;
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D : in std_logic_vector(BITCOUNT-1 downto 0);
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Q : out std_logic_vector(BITCOUNT-1 downto 0)
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);
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end FlipFlopDVector;
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architecture FlipFlopDVectorArch of FlipFlopDVector is
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begin
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ff: process( CLK )
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begin
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if( CLK'event and CLK = '0' ) then
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if( RESET = '1' ) then
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Q <= (BITCOUNT-1 downto 0 => '0');
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else
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Q <= D;
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end if;
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end if;
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end process;
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end FlipFlopDVectorArch;
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