41 lines
895 B
VHDL
41 lines
895 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity ZeroCheck is
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port(
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X, Y: in std_logic_vector(31 downto 0);
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isZero: out std_logic
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);
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end ZeroCheck;
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architecture ZeroCheckArch of ZeroCheck is
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component EqualCheck is
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generic( BITCOUNT: integer := 8 );
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port(
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X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
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isEqual: out std_logic
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);
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end component;
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signal xSign: std_logic;
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signal ySign: std_logic;
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signal xAbs: std_logic_vector(30 downto 0);
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signal yAbs: std_logic_vector(30 downto 0);
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signal isSameAbsValue: std_logic;
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signal isSameSign: std_logic;
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begin
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xSign <= X(31);
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ySign <= Y(31);
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xAbs <= X(30 downto 0);
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yAbs <= Y(30 downto 0);
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isSameSign <= xSign xnor ySign;
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AbsCheck: EqualCheck
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generic map ( BITCOUNT => 31 )
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port map (X => xAbs, Y => yAbs, isEqual => isSameAbsValue);
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isZero <= (not isSameSign) and isSameAbsValue;
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end ZeroCheckArch;
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