28 lines
541 B
VHDL
28 lines
541 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Swap is
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generic(BITCOUNT : integer := 8);
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port(
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X_IN, Y_IN : in std_logic_vector((BITCOUNT-1) downto 0);
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SW : in std_logic;
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X_OUT, Y_OUT : out std_logic_vector((BITCOUNT-1) downto 0)
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);
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end Swap;
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architecture SwapArch of Swap is
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begin
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SWAP_PRO: process(X_IN, Y_IN, SW)
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begin
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for i in (BITCOUNT-1) downto 0 loop
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X_OUT(i) <= (not(SW) and X_IN(i)) or (SW and Y_IN(i));
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Y_OUT(i) <= (not(SW) and Y_IN(i)) or (SW and X_IN(i));
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end loop;
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end process;
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end SwapArch;
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