35 lines
680 B
VHDL
35 lines
680 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity OutputSelector is
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port(
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IS_NAN : in std_logic;
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IS_ZERO : in std_logic;
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IEEE_754_SUM : in std_logic_vector(31 downto 0);
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RESULT : out std_logic_vector(31 downto 0)
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);
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end OutputSelector;
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architecture OutputSelectorArch of OutputSelector is
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signal NAN_OUT : std_logic_vector(31 downto 0);
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begin
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NAN_OUT <= "0" & "11111111" & "10000000000000000000000";
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SELECT_PROCESS : process (IS_NAN, IS_ZERO, IEEE_754_SUM, NAN_OUT)
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begin
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for i in 31 downto 0 loop
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RESULT(i) <= (not(IS_NAN) and not(IS_ZERO) and IEEE_754_SUM(i)) or (IS_NAN and NAN_OUT(i));
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end loop;
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end process;
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end OutputSelectorArch;
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