43 lines
866 B
VHDL
43 lines
866 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity PrepareForShift is
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port(
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X, Y: in std_logic_vector(31 downto 0);
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DIFF_EXP: out std_logic_vector(8 downto 0);
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SW: out std_logic
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);
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end PrepareForShift;
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architecture PrepareForShiftArch of PrepareForShift is
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signal LT: std_logic;
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signal EQ: std_logic;
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component Comparator is
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generic( BITCOUNT: integer := 8 );
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port(
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xT, yT: in std_logic_vector((BITCOUNT-1) downto 0);
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needSwap: out std_logic
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);
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end component;
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begin
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C: Comparator
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port map (xT => X(22 downto 0), yT => Y(22 downto 0), needSwap => LT);
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--istaziare sommatore la cui uscita va mappata in X(31 downto 23), Y(31 downto 23), DIFF_EXP
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EQ <= '0';
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O: process (DIFF_EXP)
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begin
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for i in 8 downto 0 loop
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EQ <= EQ or DIFF_EXP(i);
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end loop;
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end process;
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SW <= DIFF_EXP(8) or (EQ and LT);
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end PrepareForShiftArch;
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