2019-08-27 17:16:04 +02:00
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity OperationCheck is
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2019-08-29 18:08:25 +02:00
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2019-08-27 17:16:04 +02:00
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port(
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X_SIGN, Y_SIGN : in std_logic;
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OP, RES_SIGN : out std_logic
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);
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2019-08-29 18:08:25 +02:00
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2019-08-27 17:16:04 +02:00
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end OperationCheck;
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architecture OperationCheckArch of OperationCheck is
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begin
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2019-08-29 18:08:25 +02:00
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2019-08-27 17:16:04 +02:00
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OP <= X_SIGN xor Y_SIGN;
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RES_SIGN <= X_SIGN;
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end OperationCheckArch;
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