84 lines
5.3 KiB
Plaintext
84 lines
5.3 KiB
Plaintext
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#-----------------------------------------------------------
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# PlanAhead v14.7 (64-bit)
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# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
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# Start of session at: Sat Aug 24 14:51:32 2019
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# Process ID: 7025
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# Log file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.log
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# Journal file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.jou
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#-----------------------------------------------------------
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INFO: [Common 17-78] Attempting to get a license: PlanAhead
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INFO: [Common 17-290] Got license for PlanAhead
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INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
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Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
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Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
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start_gui
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source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl
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# create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3
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# set srcset [get_property srcset [current_run -impl]]
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# set_property design_mode GateLvl $srcset
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# set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ]
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# add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} }
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# set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset]
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Adding file '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf' to fileset 'constrs_1'
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# add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]]
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# link_design
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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Design is defaulting to project part: xa6slx4csg225-3
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Release 14.7 - ngc2edif P.20131013 (lin64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Release 14.7 - ngc2edif P.20131013 (lin64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Reading design SpecialCasesCheck.ngc ...
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WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf,
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ignored.
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Processing design ...
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Preping design's networks ...
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Preping design's macros ...
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finished :Prep
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Writing EDIF netlist file SpecialCasesCheck.edif ...
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ngc2edif: Total memory usage is 103004 kilobytes
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Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
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Finished Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
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Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockRegion.xml
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Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockBuffers.xml
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Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
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Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/csg225/Package.xml
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Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
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Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
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Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
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Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
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Finished Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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Phase 0 | Netlist Checksum: 684e9dfa
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link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2835.180 ; gain = 156.531
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# read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd"
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Release 14.7 - xdl P.20131013 (lin64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
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Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
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"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3
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Successfully converted design '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd' to '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xdl'.
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INFO: [Designutils 20-669] Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
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INFO: [Designutils 20-658] Finished Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
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INFO: [Designutils 20-671] Placed 103 instances
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read_xdl: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2835.180 ; gain = 0.000
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# if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} {
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# puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo"
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# }
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exit
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ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
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HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR
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HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR
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HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR
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HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR
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(See /home/Luca/ISE/IEEE754Adder/planAhead_pid7025.debug)
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ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
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INFO: [Common 17-206] Exiting PlanAhead at Sat Aug 24 14:52:27 2019...
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INFO: [Common 17-83] Releasing license: PlanAhead
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