22 lines
796 B
Plaintext
22 lines
796 B
Plaintext
|
Release 14.7 - netgen P.20131013 (lin64)
|
||
|
|
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||
|
|
|
||
|
|
Command Line: netgen -intstyle ise -ar Structure -tm SpecialCasesCheck -w -dir
|
||
|
|
netgen/synthesis -ofmt vhdl -sim SpecialCasesCheck.ngc
|
||
|
|
SpecialCasesCheck_synthesis.vhd
|
||
|
|
|
||
|
|
Reading design 'SpecialCasesCheck.ngc' ...
|
||
|
|
Flattening design ...
|
||
|
|
Processing design ...
|
||
|
|
Preping design's networks ...
|
||
|
|
Preping design's macros ...
|
||
|
|
Writing VHDL netlist
|
||
|
|
'/home/Luca/ISE/IEEE754Adder/netgen/synthesis/SpecialCasesCheck_synthesis.vhd'
|
||
|
|
...
|
||
|
|
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
|
||
|
|
simulation primitives and has to be used with UNISIM library for correct
|
||
|
|
compilation and simulation.
|
||
|
|
Number of warnings: 0
|
||
|
|
Number of info messages: 1
|
||
|
|
Total memory usage is 314432 kilobytes
|