32 lines
410 B
VHDL
32 lines
410 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity FlipFlopD is
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port(
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CLK : in std_logic;
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RESET : in std_logic;
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D : in std_logic;
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Q : out std_logic
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);
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end FlipFlopD;
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architecture FlipFlopDArch of FlipFlopD is
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begin
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ff: process( CLK )
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begin
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if( CLK'event and CLK = '0' ) then
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if( RESET = '1' ) then
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Q <= '0';
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else
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Q <= D;
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end if;
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end if;
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end process;
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end FlipFlopDArch;
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