42 lines
766 B
VHDL
42 lines
766 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity CarryLookAhead is
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port(
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X, Y : in std_logic_vector(47 downto 0);
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OP : in std_logic;
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RESULT : out std_logic_vector(47 downto 0);
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OVERFLOW : out std_logic
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);
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end CarryLookAhead;
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architecture CarryLookAheadArch of CarryLookAhead is
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--signal OVERFLOW_TMP : std_logic;
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component AddSub is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
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IS_SUB : in std_logic := '0';
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RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
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OVERFLOW : out std_logic
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);
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end component;
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begin
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CLA : AddSub
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generic map (BITCOUNT => 48)
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port map (X => X, Y => Y, IS_SUB => OP, RESULT => RESULT, OVERFLOW => OVERFLOW);
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end CarryLookAheadArch;
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